1. Introduction to Linear Regulators and Switching Regulators
of the Buck Boost and Inverting Types
In this guide, we describe many wellknown topologies (elemental building
blocks) that are commonly used to implement linear and switching power
supply designs. Each topology has both common and unique properties,
and the experienced designer will choose the topology best suited for
the intended application. However, for those engineers just starting
in this area, the choice may appear rather daunting. It is worth spending
some time to develop a basic understanding of the properties, because
the correct initial choice will avoid wasting time on a topology that
may not be the best for the application.
We will see that some topologies are best used for AC/DC offline converters
at lower output powers (say, < 200W),whereas others will be better
at higher output powers. Again some will be a better choice for higher
AC input voltages (say, = 220 VAC), whereas others will be better at
lower AC input voltages. In a similar way, some will have advantages
for higher DC output voltages (say, > 200V), yet others are preferred
at lower DC voltages. For applications where several output voltages
are required, some topologies will have a lower parts count or may offer
a tradeoff in parts counts versus reliability, while input or output
ripple and noise requirements will also be an important factor.
Further, some topologies have inherent limitations that require additional
or more complex circuitry, whereas the performance of others can become
difficult to analyze in some situations.
So we should now see how helpful it can be in our initial design choice
to have at least a working knowledge of the merits and limitations of
all the basic topologies. A poor initial choice can result in performance
limitation and perhaps in extended design time and cost. Hence it is
well worth the time and effort to get to know the basic performance parameters
of the various topologies.
In this first section, we describe some of the earliest and most fundamental
building blocks that form the basis of all linear and switching power
systems. These include the following regulators:
• Linear regulator
• Buck regulator
• Boost regulator
• Inverting regulator (also known as flyback or buckboost)
We describe the basic operation of each type, show and explain the various
waveforms, and describe the merits and limitations of each topology.
The peak transistor currents and voltage stresses are shown for various
output power and input voltage conditions. We look at the dependence
of input current on output power and input voltage.
We examine efficiency, DC and AC switching losses, and some typical
applications.
2. Linear Regulatorthe Dissipative Regulator
2.1 Basic Operation
To demonstrate the main advantage of the more complex switching regulators,
the discussion starts with an examination of the basic properties of
what preceded themthe linear or seriespass regulator.
FIG. 1a shows the basic topology of the linear regulator. It consists
of a transistor Q1 (operating in the linear, or nonswitchingmode) to
form an electrically variable resistance between the DC source (Vdc)
developed by the 60Hz isolation transformer, rectifiers, and storage
capacitor C f , and the output terminal at Vo that is connected to the
external load (not shown).
In FIG. 1a, an error amplifier senses the DC output voltage Vo via
a sampling resistor network R1, R2 and compares it with a reference voltage
Vref. The error amplifier output drives the base of the seriespass power
transistor Q1 via a drive circuit. The phasing is such that if the DC
output voltage Vo tends to increase (say, as a result of either an increase
in input voltage or a decrease in output load current), the drive to
the base of the seriespass transistor is reduced.
This increases the resistance of the seriespass element Q1 and hence
controls the output voltage so that the sampled output continues to track
the reference voltage. This negativefeedback loop works in the reverse
direction for any decreases in output voltage, such that the error amplifier
increases the drive to Q1 decreasing the collectorto emitter resistance,
thus maintaining the value of Vo constant.
FIG. 1 (a) The linear regulator. The waveform shows the ripple normally
present on the unregulated DC input (Vdc). Transistor Q1, between the
DC source at Cf and the output load at Vo , acts as an electrically variable
resistance. The negativefeedback loop via the error amplifier alters
the effective resistance of Q1 and will keep Vo constant, providing the
input voltage sufficiently exceeds the output voltage. (b) FIG. 1b
shows the minimum inputoutput voltage differential (or headroom) required
in a linear regulator. With a typical NPN seriespass transistor, a minimum
inputoutput voltage differential (headroom) of at least 2.5 V is required
between Vo and the bottom of the C f input ripple waveform at minimum
Vac input.
In general, any change in input voltagedue to, for example, AC input
line voltage change, ripple, steadystate changes in the input or output,
and any dynamic changes resulting from rapid load changes over its designed
tolerance bandis absorbed across the seriespass element. This maintains
the output voltage constant to an extent determined by the gain in the
openloop feedback amplifier.
Switching regulators have transformers and fast switching actions that
can cause considerable RFI noise. However, in the linear regulator the
feedback loop is entirely DCcoupled. There are no switching actions
within the loop. As a result, all DC voltage levels are predictable and
calculable. This lower RFI noise can be a major advantage in some applications,
and for this reason, linear regulators still have a place in modern power
supply applications even though the efficiency is quite low. Also since
the power losses are mainly due to the DC current and the voltage across
Q1, the loss and the overall efficiency are easily calculated.
2.2 Some Limitations of the Linear Regulator
This simple, DCcoupled seriespass linear regulator was the basis for
a multibilliondollar power supply industry until the early 1960s.
However, in simple terms, it has the following limitations:
• The linear regulator is constrained to produce only a lower regulated
voltage from a higher nonregulated input.
• The output always has one terminal that is common with the input.
This can be a problem, complicating the design when DC isolation is required
between input and output or between multiple outputs.
• The raw DC input voltage (Vdc in FIG. 1a) is usually de rived
from the rectified secondary of a 60Hz transformer whose weight and
volume was often a serious system constraint.
• As shown next, the regulation efficiency is very low, resulting in
a considerable power loss needing large heat sinks in relatively large
and heavy power units.
2.3 Power Dissipation in the SeriesPass Transistor
A major limitation of a linear regulator is the inevitable and large
dissipation in the seriespass element. It is clear that all the load
current must pass through the pass transistor Q1, and its dissipation
will be (Vdc  Vo )( Io ). The minimum differential (Vdc  Vo ), the
headroom, is typically 2.5 V for NPN pass transistors. Assume for now
that the filter capacitor is large enough to yield insignificant ripple.
Typically the raw DC input comes from the rectified secondary of a 60Hz
trans former. In this case the secondary turns can always be chosen so
that the rectified secondary voltage is near Vo + 2.5 V when the input
AC is at its low tolerance limit. At this point the dissipation in Q1
will be quite low.
However, when the input AC voltage is at its high tolerance limit, the
voltage across Q1 will be much greater, and its dissipation will be larger,
reducing the power supply efficiency. Due to the minimum 2.5volt headroom
requirement, this effect is much more pronounced at lower output voltages.
This effect is dramatically demonstrated in the following examples.
We will assume an AC input voltage range of ±15%. Consider three examples
as follows:
• Output of 5V at 10A
• Output of 15 V at 10 A
• Output of 30 V at 10 A
Assume for now that a large secondary filter capacitor is used such
that ripple voltage to the regulator is negligible. The rectified secondary
voltage range (Vdc) will be identical to the AC input voltage range of
±15%. The transformer secondary voltages will be chosen to yield (Vo
+ 2.5 V) when the AC input is at its low tolerance limit of 15%. Hence,
the maximum DC input is 35% higher when the AC input is at its maximum
tolerance limit of +15%. This yields the following:
It is clear from this example that at lower DC output voltages the efficiency
will be very low. In fact, as shown next, when realistic input line ripple
voltages are included, the efficiency for a 5volt output with a line
voltage range of ±15% will be only 32 to 35%.
2.4 Linear Regulator Efficiency vs. Output Voltage
We will consider in general the range of efficiency expected for a range
of output voltages from 5 V to 100 V with line inputs ranging from ±5
to ±15% when a realistic ripple value is included.
Assume the minimum headroom is to be 2.5 V, and this must be guaranteed
at the bottom of the input ripple waveform at the lower limit of the
input AC voltages range, as shown in FIG. 1b. Regulator efficiency
can be calculated as follows for various assumed input AC tolerances
and output voltages.
Let the input voltage range be ±T% about its nominal. The trans former
secondary turns will be selected so that the voltage at the bottom of
the ripple waveform will be 2.5 V above the desired output voltage when
the AC input is at its lower limit.
Let the peaktopeak ripple voltage be Vr volts. When the input AC is
at its low tolerance limit, the average or DC voltage at the input to
the pass transistor will be
Vdc = (Vo + 2.5 + Vr /2) volts
When the AC input is at its high tolerance limit, the DC voltage at
the input to the seriespass element is
FIG. 2 Linear regulator efficiency versus output voltage. Efficiency
shown for maximum Vac input, assuming a 2.5V headroom is maintained
at the bottom of the ripple waveform at minimum Vac input. Eight volts
peaktopeak ripple is assumed at the top of the filter capacitor. (From
Eqn. 2)
The maximum achievable worstcase efficiency (which occurs at maximum
input voltage and hence maximum input power) is
This is plotted in FIG. 2 for an assumed peaktopeak (p/p) ripple
voltage of 8 V. It will be shown that in a 60Hz fullwave rectifier,
the p/p ripple voltage is8Vifthe filter capacitor is chosen to be of
the order of 1000 microfarads (µF) per ampere of DC load current, an
industry standard value.
It can be seen in FIG. 2 that even for 10V outputs, the efficiency
is less than 50% for a typical AC line range of ±10%. In general it is
the poor efficiency, the weight, the size, and the cost of the 60Hz
input transformer that was the driving force behind the development of
switching power supplies.
However, the linear regulator with its lower electrical noise still
has applications and may not have excessive power loss. For example,
if a reasonably preregulated input is available (frequently the case
in some of the switching configurations to be shown later), a liner regulator
is a reasonable choice where lower noise is required. Complete integratedcircuit
linear regulators are available up to 3Aoutput in single plastic packages
and up to 5 A in metalcase integrated circuit packages. However, the
dissipation across the internal series pass transistor can still become
a problem at the higher currents. We now show some methods of reducing
the dissipation.
2.5 Linear Regulators with PNP SeriesPass Transistors for Reduced
Dissipation
Linear regulators using PNP transistors as the seriespass element can
operate with a minimum headroom down to less than 0.5 V. Hence they can
achieve better efficiency. Typical arrangements are shown in FIG. 3.
With an NPN seriespass element configured as shown in FIG. 3a,
the base current (Ib ) must come from some point at a potential higher
than Vo + Vbe, typically Vo + 1 volts. If the base drive comes through
a resistor as shown, the input end of that resistor must come from a
voltage even higher than Vo +1. The typical choice is to supply the base
current from the raw DC input as shown.
A conflict now exists because the raw DC input at the bottom of the
ripple waveform at the low end of the input range cannot be per mitted
to come too close to the required minimum base input voltage (say, Vo
+ 1). Further, the base resistor Rb would need to have a very low value
to provide sufficient base current at the maximum output current. Under
these conditions, at the high end of the input range (when Vdc  Vo is
much greater), Rb would deliver an excessive drive current; a significant
amount would have to be diverted away into the current amplifier, adding
to its dissipation. Hence a compromise is required. This is why the minimum
header voltage is selected to be typically 2.5 V in this arrangement.
It maintains a more constant current through Rb over the range of input
voltage.
However, with a PNP seriespass transistor (as in FIG. 3b), this
problem does not exist. The drive current is derived from the common
negative line via the current amplifier. The minimum header voltage is
defined only by the knee of the Ic versus Vce characteristic of the pass
transistor. This may be less than 0.5V, providing higher efficiency particularly
for lowvoltage, highcurrent applications.
Although integratedcircuit linear regulators with PNP pass transistors
are now available, they are intrinsically more expensive because the
fabrication is more difficult.
FIG. 3 (a) A linear regulator with an NPN seriespass transistor.
In this example, the base drive is taken from Vdc via a resistor Rb .
A typical minimum voltage of 1.5 V is required across Rb to supply the
base current, which when added to the baseemitter drop makes a minimum
header voltage of 2.5 V. (b) Linear regulator with a PNP seriespass
transistor. In this case the base drive (Ib ) is derived from the negative
common line via the drive circuit. The header voltage is no longer restricted
to a minimum of 2.5 V, and much lower values are possible.
Similar results can be obtained with NPN transistors by fitting the
transistor in the negative return line. This requires the positive line
to be the common line. (Normally this would not be a problem in single
output supply.)
This completes our overview of linear regulators and serves to demonstrate
some of the reasons for moving to the more complicated switching methods
for modern, lowweight, small, and efficient power systems.
3. Switching Regulator Topologies
3.1 The Buck Switching Regulator
The high dissipation across the seriespass transistor in a linear regulator
and the large 60Hz transformer required for line operation made linear
regulators unattractive for modern electronic applications.
Further, the high power loss in the series device requires a large heat
sink and large storage capacitors and makes the linear power supply disproportionately
large.
As electronics advanced, integrated circuits made the electronic systems
smaller. Typically, linear regulators could achieve output power densities
of 0.2 to 0.3 W/in^3, and this was not good enough for the ever smaller
modern electronic systems. Further, linear power sup plies could not
provide the extended holdup time required for the controlled shutdown
of digital storage systems.
Although the technology was previously well known, switching regulators
started being widely used as alternatives to linear regulators only in
the early 1960s when suitable semiconductors with reasonable performance
and cost became available. Typically these new switching supplies used
a transistor switch to generate a square waveform from a nonregulated
DC input voltage. This square wave, with adjustable duty cycle, was applied
to a low pass output power filter so as to provide a regulated DC output.
Usually the filter would be an inductor (or more correctly a choke,
since it had to support some DC) and an output capacitor. By varying
the duty cycle, the average DC voltage developed across the output capacitor
could be controlled. The low pass filter ensured that the DC output voltage
would be the average value of the rectangular voltage pulses (of adjustable
duty cycle) as applied to the input of the lowpass filter. A typical
topology and waveforms are shown later in FIG. 4.
With appropriately chosen low pass inductor/capacitor (LC)filters, the
squarewave modulation could be effectively minimized, and nearripplefree
DC output voltages, equal to the average value of the dutycyclemodulated
raw DC input, could be provided. By sensing the DC output voltage and
controlling the switch duty cycle in a negativefeedback loop, the DC
output could be regulated against input line voltage changes and output
load changes.
Modern very high frequency switching supplies are currently achieving
up to 20W/in^3 compared with 0.3W/in^3 for the older linear power supplies.
Further, they are capable of generating a multiplicity of isolated output
voltages from a single input. They do not require a 50/60Hz isolation
power transformer, and they have efficiencies from 70% up to 95%. Some
DC/DC converter designers are claiming load power densities of up to
50 W/in3 for the actual switching elements.
3.1.1 Basic Elements and Waveforms of a Typical Buck Regulator
In the interest of simplicity, we describe fixedfrequency operation
for the following switching regulator examples. In such regulators the
on period of the power device (Ton) is adjusted to maintain regulation,
while the total cycle period (T) is fixed, and the frequency is thus
fixed at 1/T.
FIG. 4 Buck switching regulator and typical waveforms.
The ratio Ton/T is normally referred to as the duty ratio or duty cycle
(D) in many modern treatises. In other guides on the subject, you may
find this shown as Ton/(Ton+ Toff), where Toff is the off period of the
power device so that Ton +Toff =T. Operators D and M are also used in
various combinations but essentially refer to the same quantity.
Bear in mind that other modes of operation can be and are used. For
example, the on period can be fixed and the frequency changed, or a combination
of both may be employed.
The terms dI, di, dV, dv, dT and dt are used somewhat loosely in this
guide and normally refer to the changes _I, _V, and _t, where, for example,
in the limit,_I/_t goes to the derivative di/dt, giving the rate of change
of current with time or the slope of the waveform. Since in most cases
the waveform slopes are linear the result is the same so this becomes
a moot point.
3.1.2 Buck Regulator Basic Operation
The basic elements of the buck regulator are shown in FIG. 4.
Transistor Q1 is switched hard "on" and hard "off" in
series with the DC input Vdc to produce a rectangular voltage at point
V1. For fixed frequency dutycycle control, Q1 conducts for a time Ton
(a small part of the total switching period T).When Q1 is "on," the
voltage at V1is Vdc, assuming for the moment the "on" voltage
drop across Q1 is zero.
A current builds up in the series inductor Lo flowing toward the output.
When Q1 turns "off," the voltage at V1 is driven rapidly toward
ground by the current flowing in inductor Lo and will go negative until
it is caught and clamped at about 0.8 V by diode D1 (the socalled freewheeling
diode).
Assume for the moment that the "on" drop of diode D1 is zero.
The square voltage shown in FIG. 4b would be rectangular, ranging
between Vdc and ground, (0V)with a "high" period of Ton. The
average value of this rectangular waveform is VdcTon/T. The low pass
LoCo filter in series betweenV1 and the output tV extracts the DC component
and yields a clean, nearripplefree DC voltage at the output with a
magnitude Vo of VdcTon/T.
To control the voltage, Vo is sensed by sampling resistors R1 and R2
and compared with a reference voltage Vref in the error amplifier (EA).
The amplified DC error voltage Vea is fed to a pulsewidthmodulator
(PWM). In this example the PWM is essentially a voltage comparator with
a sawtooth waveform as the other input (see FIG. 4a).
This sawtooth waveform has a period T and amplitude typically in the
order of 3 V. The highgain PWM voltage comparator generates a rectangular
output waveform (Vwm, see FIG. 4c) that goes high at the start of
the sawtooth ramp, and goes low the instant the ramp volt age crosses
the DC voltage level from the erroramplifier output. The PWM output
pulse width (Ton) is thus controlled by the EA amplifier output voltage.
The PWM output pulse is fed to a driver circuit and used to control
the "on" time of transistor switch Q1 inside the negativefeedback
loop. The phasing is such that if Vdc goes slightly higher, the EA DC
level goes closer to the bottom of the ramp, the ramp crosses the EA
output level earlier, and the Q1 "on" time decreases, maintaining
the output voltage constant. Similarly, if Vdc is reduced, the "on" time
of Q1 increases to maintain Vo constant. In general, for all changes,
the "on" time of Q1 is controlled so as to make the sampled
DC output voltage Vo R2/(R1 + R2) closely track the reference voltage
Vref.
3.2 Typical Waveforms in the Buck Regulator
In general, the major advantage of the switching regulator technique
over its linear counterpart is the elimination of the power loss intrinsic
in the linear regulator pass element.
In the switching regulator the pass element is either fully "on" (with
very little power loss) or fully "off" (with negligible power
loss). The buck regulator is a good example of thisit has low internal
losses and hence high power conversion efficiency.
However, to fully appreciate the subtleties of its operation, it is
necessary to understand the waveforms and the magnitude and timing of
the currents and voltages throughout the circuit. To this end we will
look in more detail at a full cycle of events starting when Q1 turns
fully "on." For convenience we will assume ideal components
and steadystate conditions, with the amplitude of the input voltage
Vdc constant, exceeding the output voltage Vo , which is also constant.
When Q1 turns fully "on," the supply voltage Vdc will appear
across the diode D1 at point V1. Since the output voltage Vo is less
than Vdc, the inductor Lo will have a voltage impressed across it of
(Vdc  Vo ).
With a constant voltage across the inductor, its current rises linearly
at a rate given by di/dt = (Vdc Vo )/Lo . (This is shown in FIG. 4d
as a ramp that sits on top of the step current waveform.) When Q1 turns "off," the
voltage at point V1 is driven toward zero because it is not possible
to change the previously established inductor current instantaneously.
Hence the voltage polarity across Lo immediately reverses, trying to
maintain the previous current.
(This polarity reversal is often referred to as the flyback or inductive
kickback effect of the inductor.) Without diode D1, V1 would have gone
very far negative, but with D1 fitted as shown, as the V1 volt age passes
through zero, D1 conducts and clamps the left side of Lo at one diode
drop below ground. The voltage across the inductor has now reversed,
and the current in the inductor and D1 will ramp down, returning to its
original starting value, during the "off" period of Q1.
More precisely, when Q1 turns "off," the current I2 (which
had been flowing in Q1, Lo and the output capacitor Co and the load just
prior to turning "off") is diverted and now flows through diode
D1, Lo and the output capacitor and load, as shown in FIG. 4e. The
voltage polarity across Lo has reversed with a magnitude of (Vo + 1).
The current in Lo now ramps down linearly at a rate defined by the equation
di/dt =(Vo +1)/Lo . This is the downward ramp that sits on a step in
FIG. 4e.Under steadystate conditions, at the end of the Q1 "off" time,
the current in Lo will have fallen to I1 and is still flowing through
D1, Lo and the output capacitor and load.
Note:
Notice the input current is discontinuous with a pulselike characteristic,
whereas the output current remains nearly continuous with some relatively
small ripple component depending on the value of Lo and Co.
Now when Q1 turns "on" again, it initially supplies current
into the cathode of D1, displacing its previous forward current. While
the current in Q1 rises toward the previous value of I1, the forward
D1 current will be displaced, and V1 rises to near Vdc, backbiasing
D1.
Because Q1 is switched "on" hard, this recovery process is
very rapid, typically less than 1 µs.
Notice that the current in Lo is the sum of the Q1 current when it is "on" (see
FIG. 4d) plus the D1 current when Q1 is "off." This is
shown in FIG. 4 f as IL,o . It has a DC component and a triangular
waveform ripple component (I2  I1) centered on the mean DC out put current
Io . Thus the value of the current at the center of the ramp in Figure
1.4d and 1.4e is simply the DC mean output current Io . As the load resistance
and hence load current is changed, the center of the ramp (the mean value)
in either FIG. 4d or 1.4e moves, but the slopes of the ramps remain
constant, because during the Q1 "on" time, the ramp rate in
Lo remains the same at (Vdc Vo )/Lo , and during the Q1 "off" time,
it remains the same at (Vo + 1)/L as the load current changes, because
the input and output voltages remain constant.
Because the pp ripple current remains constant regardless of the mean
output current, it will be seen shortly that when the DC current Io is
reduced to the point where the lower value of the ripple current in Figure
4d and 4e just reaches zero (the critical load current), there will
be a drastic change in performance. (This will be discussed in more detail
later.)
3.3 Buck Regulator Efficiency
To get a general feel for the intrinsic power loss in the buck regulator
compared with a linear regulator, we will start by assuming ideal components
for transistor Q1 and diode D1 in both topologies. Using the currents
shown in FIG. 4d and 1.4e, the typical conduction losses in Q1 and
freewheeling diode D1 can be calculated and the efficiency obtained.
Notice that when Q1 is "off," it operates at a maximum volt
age of Vdc but at zero current. When Q1 is "on," current flows,
but the voltage across Q1 is zero. At the same time, D1 is reversebiased
at a voltage of Vdc but has zero current. (Clearly, if Q1 and D1 were
ideal components, the currents would flow through Q1 and D1 with zero
voltage drop, and the loss would be zero.) Hence unlike the linear regulator,
which has an intrinsic loss even with ideal components, the intrinsic
loss in a switching regulator with ideal components is zero, and the
efficiency is 100%. Thus in the buck regulator, the real efficiency depends
on the actual performance of the components. Since improvements are continually
being made in semiconductors, we will see ever higher efficiencies.
To consider more realistic components, the losses in the buck circuit
are the conduction losses in Q1 and D1 and the resistive winding loss
in the choke. The conduction losses, being related to the mean DC currents,
are relatively easy to calculate. To this we must add the AC switching
losses in Q1 and D1, and the AC induced core loss in the inductor, so
the switching loss is more difficult to establish.
The switching loss in Q1 during the turn "on" and turn "off" transitions
is a result of the momentary overlap of current and voltage during the
switching transitions. Diode D1 also has switching loss associated with
the reverse recovery action of the diode, where again there is a condition
of voltage and current stress during the transitions.
The ripple wave for min the inductor Lo results in hysteretic and eddy
current loss in the core material. We will now calculate some typical
losses.
3.3.1 Calculating Conduction Loss and ConductionRelated Efficiency
By neglecting secondorder effects and AC switching losses, the conduction
loss can be quite easily calculated. It can be seen from FIG. 4d
and 4e that the average currents in Q1 and D1 during their conduction
times of Ton and Toff are the values at the center of the ramps or Io
, the mean DC output current. These currents flow at a forward voltage
of about 1 V over a wide range of currents. Thus conduction losses will
be approximately
Therefore, by neglecting AC switching losses, the conductionrelated
efficiency would be
3.4 Buck Regulator Efficiency Including AC Switching Losses
The switching loss is much more difficult to establish, because it depends
on many variables relating to the performance of the semiconductors and
to the methods of driving the switching devices. Other variables, related
to the actual power circuit designs, include the action of any snubbers,
load line shaping, and energy recovery arrangements. It depends on what
the designer may choose to use in a particular design. Unless all these
things are considered, any calculations are at best only a very rough
approximation and can be far from the real values found in the actual
design, particularly at high frequencies with the very fast switching
devices now available.
Many semiconductor manufacturers now provide switching loss equations
for their switching devices when recommended drive conditions are used,
particularly the modern fast IGBTs (Insulated Gate Bipolar Transistors).
Some fast digital oscilloscopes claim that they will actually measure
switching loss, providing the realtime device current and voltage is
accurately provided to the oscilloscope. (Doing this can also be problematical
at very high frequency.) The method I prefer, which is unquestionably
accurate, is to measure the temperature rise of the device in question
in a working model. The model must include all the intended snubbers
and load line shaping circuits, etc.
Replacing the AC current in the device with a DC current to obtain the
same temperature rise will provide a direct indication of power loss
by simple DC power measurements. This method also allows easy optimization
of the drive and load line shaping, which can be dynamically adjusted
during operation for minimum temperature rise and hence minimum switching
loss.
Alternatingcurrent switching loss (or voltage/current overlap loss)
calculation depends on the shape and timing of the rising and falling
voltage and current waveforms. An idealized linear examplewhich is unlikely
to exist in practiceis shown in FIG. 5a and serves to illustrate
the principle.
FIG. 5a shows the bestcase scenario. At the turn "on" of
the switching device, the voltage and current start changing simultaneously
and reach their final values simultaneously. The current waveform goes
from 0 to Io , and voltage across Q1 goes from a maximum of Vdc down
to zero. The average power during this switching transition is
P(Ton)
= _ Ton
0 IV dt = IoVdc/6, and the power averaged over one complete period is
(IoVdc/6)(Ton/T).
Assuming the same scenario of simultaneous starting and ending points
for the current fall and voltage rise wave forms at the turn "off" transition,
the voltage/current overlap dissipation at this transition is given by
P(Toff) = _ Toff
0 IV dt = IoVdc/6 and this power averaged over one complete cycle is
(IoVdc/6)(Toff/T).
FIG. 5 Idealized transistor switching waveforms. (a) Waveforms show
the voltage and current transitions starting and ending simultaneously.
(b) Waveforms show the worstcase scenario, where at turn "on" voltage
remains constant at Vdc(max) until current reaches its maximum. At turn "off," the
current remains constant at Io until Q1 voltage reaches its maximum of
Vdc.
Assuming Ton = Toff = Ts , the total switching losses (the sum of turn "off" and
turn "on" losses) are Pac = (Vdc Io Ts )/3T, and efficiency
is calculated as shown next in Eqn. 4.
It would make an interesting comparison to calculate the efficiency
of the buck regulator and compare it with that of a linear regulator.
Assume the buck regulator provides 5 V from a 48V DC input at 50kHz
switching frequency (T =20 µs).
If there were no AC switching losses and a switching transition period
Ts of 0.3 µs were assumed, Eqn. 3 would give a conduction loss efficiency
of
If switching losses for the bestcase scenario as shown in FIG. 5a
were assumed, for Ts = 0.3 µs and T = 20 µs, Eqn. 4 would give a switchingrelated
efficiency of
If a worstcase scenario were assumed (which is closer to reality),
as shown in FIG. 5b, efficiencies would lower. In FIG. 5b it
is assumed that at turn "on" the voltage across the transistor
remains at its maximum value (Vdc) until the onturning current reaches
its maximum value of Io . Then the voltage starts falling. To a close
approximation, the current rise time Tcr will equal voltage fall time.
Then the turn "on" switching losses will be
also for Tcr = Tvf = Ts , P(Ton) = Vdc Io (Ts/T).
At turn "off" (as seen in FIG. 5b), we may assume that
current hangs on at this maximum value Io until the voltage has risen
to its maximum value of Vdc in a time Tvr. Then current starts falling
and reaches zero in a time Tcf. The total turn "off" dissipation
will be
With Tvr = Tcf = Ts , P(Toff) = Vdc Io (Ts/T). The total AC losses (the
sum of the turn "on" plus the turn "off" losses)
will be:
...and the total losses (the sum of DC plus AC losses) will be ...
...and the efficiency will be ...
Hence in the worstcase scenario, for the same buck regulator with Ts
= 0.3 µs, the efficiency from Eqn. 7 will be ...
Comparing this with a linear regulator doing the same job (bringing
48 V down to 5 V), its efficiency (from Eqn. 1) would be Vo /Vdc(max)
, or 5/48; this is only 10.4% and is clearly unacceptable.
3.5 Selecting the Optimum Switching Frequency
We have seen that the output voltage of the buck regulator is given
by the equation Vo = VdcTon/T. We must now decide on a value for this
period and hence the operating frequency.
The initial reaction may be to minimize the size of the filter components
Lo , Co by using as high a frequency as possible. However, using higher
frequencies does not necessarily minimize the overall size of the regulator
when all factors are considered.
We can see this better by examining the expression for the AC losses
shown in Eqn. 5, Pac = 2Vdc Io Ts T . We see that the AC losses are inversely
proportional to the switching period T. Further, this equation only shows
the losses in the switching transistor; it neglects losses in the freewheeling
diode D1 due to its finite reverse recovery time (the time required for
the diode to cease conducting reverse current, measured from the instant
it has been subjected to a reverse bias volt age). The freewheeling
diode can dissipate significant power and should be of the ultrafast
soft recovery type with minimum recovered charge. The reverse recovery
time will typically be 35 ns or less.
In simple terms, the more switching transitions there are in a particular
period, the more switching loss there will be. As a result there is a
tradeoffdecreasing the switching period T (increasing the switching
frequency) may well decrease the size of the filter elements, but it
will also add to the total losses and may require a larger heat sink.
In general, although the overall volume of the buck regulator will be
lower at a higher frequency, the increase in the switching loss and the
more stringent highfrequency layout and componentselection requirements
make the final choice a compromise among all the op posing elements.
Note:
The picture is constantly changing as better, lower cost, and faster
transistors and diodes are developed. My choice at the present stage
of the technology is to design below100 kHz, as this is less demanding
on component selection, layout, and transformer/inductor designs. As
a result it is probably lower cost. Generally speaking, higher frequencies
absorb more development time and require more experience. However,
efficient commercial designs are on the market operating well into the
MHz range. The final choice is up to the designer, and I hesitate to
recommend a limit because technology is constantly changing toward higher
frequency operation.
cont. to part 2 >>
Also see:
