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3.6 Design Examples
3.6.1 Buck Regulator Output Filter Inductor (Choke) Design
The output inductor and capacitor may be considered a low pass filter, and it is normally treated in this way for transfer function and loop compensation calculations.
However, at this stage, the reader may prefer to look upon the inductor as a device that tends to maintain the current reasonably constant during the switching action. (That is, it stores energy when the power device is "on" and transfers this energy to the output when the power device is "off.") I prefer the term choke for the power inductor, because in this application it must support an element of DC current as well as the applied AC voltage stress. It will be shown later (Section 7) that the design of pure inductors (with zero DC current component) is quite different from the design of chokes, with their relatively large DC current component.
In the following section we outline the parameters that control the design and selection of this critical part.
The current waveform of the output inductor (choke) is shown in Figure 4f, and its characteristic "dual ramp" shape is defined in Section 3.2. Notice that the current amplitude at the center of the ramp is the mean value equal to the DC output current Io.
We have seen that as the DC output load current decreases, the slope of the ramp remains constant (because the voltage across Lo remains constant). But as the mean load current decreases, the ripple current waveform moves down toward zero.
At a load current of half the peak-to-peak magnitude of the ramp, Io = ( I2 - I1)/2dI, the lower point of the ramp just touches zero.
At this point, the current in the inductor is zero and its stored energy is zero. (The inductor is said to have "run dry.") If the load current is further reduced, there will be a period when the inductor current remains at zero for a longer period and the buck regulator enters into the "discontinuous current" operating mode. This is an important transition because a drastic change occurs in the current and voltage waveforms and in the closed loop transfer function.
This transition to the discontinuous mode can be seen in the real time oscilloscope picture of FIG. 6a. This shows the power switch current waveforms for a buck regulator operating at 25 kHz with an input voltage of 20 V and an output of 5 V as the load current is reduced from a nominal current of 5 A down to about 0.2 A.
The top two waveforms have the characteristic ramp-on-a-step waveshape with the step size reducing as the load current is reduced.
The current amplitude at the center of the ramp indicates the effective DC output current.
In the third waveform, where Io = 0.95 A, the step has gone and the front end of the ramp starts at zero current. This is the critical load current indicating the start of the discontinuous current mode (or run dry mode) for the inductor. Notice that in the first three waveforms, the Q1 "on" time is constant, but decreases drastically as the current is further reduced, moving deeper into the discontinuous mode.
In this example, the control loop has been able to maintain the out put voltage constant at 5 V throughout the full range of load currents, even after the inductor has gone discontinuous. Hence it would be easy to assume that there is no problem in permitting the inductor to go discontinuous. In fact there are changes in the transfer function (discussed next) that the control loop must be able to accommodate.
Further, the transition can become a major problem in the boost-type topologies discussed later.
For the buck regulator, however, the discontinuous mode is not considered a major problem. For load currents above the onset of the discontinuous made, the DC output voltage is given by Vo = V1Ton/T.
Notice the load current is not a parameter in this equation, so the voltage remains constant with load current changes without the need to change the duty ratio. (The effective output resistance of the buck regulator is very low in this region.) In practice the "on" time changes slightly as the current changes, because the forward drop across Q1 and the inductor resistance change slightly with current, requiring a small change in Ton.
If the load is further reduced so as to enter discontinuous mode, the transfer function changes drastically and the previous equation for output voltage (Vo = V1Ton/T) no longer applies. This can be seen in the bottom two waveforms of FIG. 6a. Notice the "on" time of Q1 has decreased and has become a function of the DC output current.
TIP The ratio Ton/T is normally referred to as the duty ratio D. The voltage formula for continuous operation is simply Vo = V1.D. However, for discontinuous operation, the duty ratio becomes a function of the load current, and the situation is much more complicated. In the discontinuous mode, the output voltage Vo is given by the formula
Since the control loop will maintain the output voltage constant, the effective value of the load resistance R will be inversely proportional to the load current. Hence by holding Vo,V1, L, and T constant, to maintain the voltage constant, requires that the remaining variable (the duty ratio D) must change with load current.
At the critical transition current, the transfer function will change from continuous mode in which the duty ratio remained constant with load change (zero output impedance) to the discontinuous mode in which the duty ratio must change with reducing load current (a finite output impedance). Hence in the discontinuous mode, the control loop must work much harder, and the transient performance will be degraded. .
Dynamically, at load currents above the onset of the discontinuous mode, the output L/C filter automatically accommodated out put current changers by changing the amplitude of the step part of the ramp-on-step waveforms shown in the Q1 and D1 waveforms of Figures 1.4d and 1.4e. To the first order, it could do this without changing the Q1 "on" time.
The DC output current is the time average of the Q1 and D1 ramp current. Notice that in FIG. 6a, line three and line four, that at lower currents where the inductor has gone discontinuous and the step part of the latter waveforms has gone to zero, the only way the current can decrease further is to decrease the Q1 "on" time. The negative feedback loop automatically adjusts the duty ratio to achieve this.
The dramatic change in the waveforms can be seen very clearly between FIG. 7a (for the critical current condition) and FIG. 7b (for the discontinuous condition). FIG. 7b(2) shows the D1 current going to zero just before Q1 turns "on" (the inductor has dried out and gone discontinuous).With zero current in Lo , the output voltage will seek to appear at the emitter of Q1. However, the sudden transition results in a decaying voltage "ring," at a frequency determined by Lo and the distributed capacitance looking into the D1 cathode and Q1 emitter junction at point V1. This is shown in FIG. 7b(1).
TIP Although the voltage ring is not damaging, in the interest of RFI reduction, it should be suppressed by a small R/C snubber across D1.
3.6.2 Designing the Inductor to Maintain Continuous Mode Operation
Although we have shown that operating in the discontinuous mode is not necessarily a major problem in the buck regulator, it can become a problem in some applications, particularly in boost-type topologies.
The designer has the option to design the inductor so that it remains in the continuous mode for the full range of expected (but limited) load currents, as described next.
In this example the inductor will be chosen so that the current re mains continuous if the DC output current stays above a specified minimum value. (Typically this is chosen to be around 10% of the rated load current, or 0.1 Ion, where "Ion" is defined as the nominal output current.) The inductor current ramp is dI = ( I2 -I1), as shown in FIG. 4d.
Since the onset of the discontinuous mode occurs at a DC current of half this amplitude, then
where Ion is the center of the inductor current ramp at nominal DC output current.
Since the inductor current will swing ±10% around its center value Ion, the inductor must be designed so that it does not significantly saturate at a current of at least 1.1 Ion.
Section 7, Section 7.6 provides information for the optimum design of inductors and chokes.
3.6.3 Inductor (Choke) Design
In the preceding example, continuous mode operation is required, so the current must not reach zero for the full range of load currents.
Thus the inductor must support a DC current component and should be designed as a choke.
Well-designed chokes have a low, but relatively constant, inductance under AC voltage stress and DC bias conditions. Typically chokes use either gapped ferrite cores or composite cores of various powdered ferromagnetic alloys, including powdered iron or Permalloy, a magnetic alloy of nickel and iron. Powdered cores have a distributed air-gap because they are made from a suspension of powdered ferromagnetic particles, embedded in a nonmagnetic carrier to provide a uniformly distributed air-gap. The inductor value calculated by Eqn. 8 must be designed so that it does not saturate at the specified peak current (110% of Ion). The design of such chokes is described in more detail in Section 7, Section 7.6.
The maximum range of current in the buck regulator will be determined by the choke design, the ratings of the power components, and the DC and AC losses given by Eqn. 6. To remain in continuous conduction, the minimum current must not go below10%of the rated Ion. Below this the load regulation will degrade slightly.
This wide (90%) industry standard dynamic load range results in a relatively large choke, which may not be acceptable. However, the designer has considerable flexibility of choice with some trade-offs.
If a smaller choke is chosen (say, half the value given by Eqn. 8), it will go discontinuous at one-fifth rather than one-tenth of the nominal DC output current. This will degrade the load regulation slightly, commencing at the higher minimum current. But since it has less inductance, the buck regulator will respond more quickly to dynamic load changes.
3.7 Output Capacitor
The output capacitor (Co ) shown in FIG. 4 is chosen to satisfy several requirements. Co will not be an ideal capacitor, as shown in FIG. 8. It will have a parasitic resistance Ro and inductance Lo in series with its ideal pure capacitance Co as shown. These are referred to as the equivalent series resistance (ESR) and equivalent series inductance (ESL). In general, if we consider the bulk ripple current amplitude in the series choke L f , we would expect the majority of this ripple current to flow in to the output capacitor Co .Hence the output voltage ripple will be determined by the value of the output filter capacitor, Co , its equivalent series resistance (ESR), Ro , and its equivalent series inductance (ESL), Lo.
For low-frequency ripple currents, Lo can be neglected and the out put ripple is mainly determined by Ro and Co.
The actual transition frequency depends on the design of the capacitor, and manufacturers are constantly improving. Typically it will be above 500 kHz.
So below about 500 kHz, Lo can normally be neglected. Typically Co is a relatively large electrolytic, so that at the switching frequency, the ripple voltage component contributed by Co is small compared with that contributed by Ro . Thus at the mid-frequencies, to the first order, the output ripple is closely given by the AC ripple current in L f times Ro .
More precisely, there are two ripple components due to each of Ro and Co . They are not in phase because that generated by Ro is proportional to I2 - I1 (the peak-to-peak inductor ramp current of FIG. 4 f ) and that due to Co is proportional to the integral of that current. However, for a worst-case comparison we can assume that they are in phase.
To obtain these ripple voltage components and to permit capacitor selection, it is necessary to know the values of the ESR Ro , which are seldom given by capacitor manufacturers. An examination of a number of manufacturers' catalogs shows that for the older types (aluminum electrolytic) for a large range of voltage ratings and capacitance values, RoCo tends to be constant. It ranges from 50 to 80 × 10^-6_F.
Modern low-ESR electrolytic capacitors are now de signed for this application, and the ESR values are provided by the manufacturers. If the low-ESR types are chosen, then clearly the lower ESR values should be used in the following calculations.
It is instructive to calculate the capacitive and resistive ripple components for a typical buck regulator.
Assume a design for a 25-kHz buck regulator with a step down from 20 V to 5 V with a load current Ion = 5 A. Let's require the ripple voltage to be below 50 millivolts with continuous conduction down to 10% load.
Assuming the minimum load is to be 10%, then Io(min) = 0.1Ion = 0.5 A. We will calculate L from Eqn. 8:
Now dI (the peak-to-peak ramp amplitude) is (I 2-I 1) = 0.2Ion = 1A.
If we assume the majority of the output ripple voltage will be produced by the capacitor ESR (Ro ), we can simply select a capacitor value such that the ESR will satisfy the ripple voltage as follows:
With a resistive ripple component of Vrr = 0.05 V peak-to-peak, then the required ESR Ro = Vrr/dI = 0.05/(I 2 - I 1) and Ro = 0.05_.
Using the preceding typical ESR/capacitance relationship (RoCo = 50 × 10^-6):
Note Clearly, for modern low ESR capacitors, we would use the published ESR values.
We will now calculate the ripple voltage contribution from the capacitance, (Co = 1000 µF).
Calculating the capacitive ripple voltage Vcr from FIG. 4d, it is seen that the ripple current is positive from the center of the "off" time to the center of the "on" time or for one-half of a period, or 20 µs in this example. The average value of this triangle of current is (I2 - I1)/4 = 0.25 A. This current produces a ripple voltage across the pure capacitance part C of
The ripple current below the Io line in FIG. 4 f yields another 0.005-V ripple for a total peak-to-peak capacitive ripple voltage of 0.01 V (only 10 millivolts compared with the resistive component of 50millivolts). Thus, in this particular case, the ripple due to the capacitance is relatively small compared with that due to the ESR resistor Ro and to the first order may be ignored.
In the preceding example, the filter capacitor was chosen to yield the desired peak-to-peak ripple voltage by choosing a capacitor with a suitable ESR Ro from
Using the typical relationship that the RoCo product will be near 65 × 10^-6:
The justification for this approach is demonstrated more generally in the paper by K.V. Kantak.
(1) He shows that if RoCo is larger than half the transistor "on" time and half the transistor "off" time-which is the more usual case-the output ripple is determined by the ESR resistor as shown above.
3.8 Obtaining Isolated Semi-Regulated Outputs from a Buck Regulator
Very often, low-power ancillary outputs are required for various control functions. This can be done with few additional components as shown in FIG. 9. The regulation in the additional outputs is typically of the order of 2 to 3%.
It can be seen in FIG. 4 that the return end of the regulated output voltage is common with the return end of the raw DC input. In Figure 1.9, a second winding with N2 turns is added to the output filter choke. Its output is peak-rectified with diode D2 and capacitor C2. The start of the N1, N2 windings is shown by the dots. When Q1 turns "off," the finish of N1 goes negative and is caught at one diode drop below ground by free-wheeling diode D1. Since the main output Vo is regulated against line and load changes, the reverse voltage across N1 is constant as long as the free-wheeling diode D1 continues to conduct. Using a low-forward-drop Schottky diode for D1, its forward drop remains constant at about. 0.4 V over a large range of DC output current.
Thus when Q1 turns "off," the voltage across N2 is relatively constant at N2/N1 (Vo + 0.4) volts with its dot end positive. This is peak rectified by D2 and C2 to yield Vo 2 = N2/N1(Vo + 0.4) - 0.4if D2 is also a Schottky diode. This output is independent of the supply voltage Vdc as D2 is reverse biased when Q1 turns "on." Capacitor C2 should be selected to be large enough that the ancillary voltage does not decay too much during the maximum Q1 "on" time. Since N2 and N1 are isolated from each another, the ancillary output can be isolated or referenced to any other part of the circuit.
TIP This can be a useful technique, but use it with care; notice the ancillary power is effectively stolen from the main output during the reverse recovery of the choke. Hence the main output power needs to be much larger than the total ancillary power to maintain D1 in conduction. A minimum load will be required on the main output if the ancillary outputs are to be maintained.
Notice that using the ancillary outputs to power essential parts of the control circuit can have problems, as the system may not start.
4. The Boost Switching Regulator Topology
4.1 Basic Operation
The buck regulator topology shown in FIG. 4 has the limitation that it can only produce a lower voltage from a higher voltage. For this reason it is often referred to as a step-down regulator.
The boost regulator (FIG. 10) shows how a slightly different topology can produce a higher regulated output voltage from a lower unregulated input voltage. Called a boost regulator or a ringing choke, it works as follows.
An inductor L1 is placed in series with Vdc and a switching transistor Q1 to common. The bottom end of L1 feeds current to Q1 when Q1is "on" or the output capacitor Co and load resistor through rectifying diode D1 when Q1 is "off." Assuming steady-state conditions, with the output voltage and cur rent established, when Q1 turns "on" (for a period Ton), D1 will be reverse biased and does not conduct. Current ramps up linearly in L1 to a peak value Ip = VdcTon/L1.
During the Q1 "on" time, the output current is supplied entirely from Co , which is chosen to be large enough to supply the load current for the time Ton with the specified minimum droop.
FIG. 10 Boost regulator and critical waveforms. Energy stored in L1 during the Q1 "on" time is delivered to the output via D1 at a higher output voltage when Q1 turns "off" and the polarity across L1 reverses.
When Q1 turns "off," since the current in an inductor cannot change instantaneously, the voltage across L1 reverses in an attempt to maintain the current constant. Now the lower end of L1 goes positive with respect to the input voltage. With the output voltage Vo higher than the input Vdc, L1 delivers its stored energy to Co via D1. Hence Co is boosted to a higher voltage than Vdc. This energy replenishes the charge drained away from Co when D1 was not conducting. At the same time current is also supplied to the load from Vdc via L1 and D1 during this action.
In simple terms, the output voltage is regulated by controlling the Q1 "on" time in a negative-feedback loop. If the load current increases, or the input voltage decreases, the "on" time of Q1 is automatically increased to deliver more energy to the load, or the converse. Hence, in normal operation the "on" period of Q1 is adjusted to maintain the output voltage constant.
4.2 The Discontinuous Mode Action in the Boost Regulator
TIP: The boost regulator has two quite different modes of operation depending on the conduction state of the inductor. If the inductor current reaches zero at the end of a cycle, it is said to operate in a discontinuous mode. If there is some current remaining in the inductor at the end of a cycle, it is said to be in a continuous mode of operation.
When speaking about switching regulators, the output filter capacitor is not normally included in the analysis of the converter. The output current of a switching regulator is, therefore, not the DC output current to the load, but rather the combined current that flows in the output capacitor and the load in parallel.
Notice that unlike the buck regulator, the boost regulator has a continuous input current (with some ripple current) but a discontinuous output current for all modes of operation. Hence the terms continuous and discontinuous mode refer to what is going on in the inductor.
There is a dramatic difference in the transfer function between the two modes of operation that significantly changes the transient performance and intrinsic stability. This is explained more fully in Section 12.
We will consider in more detail the action for discontinuous mode operation, in which the energy in the inductor is completely transferred to the output during the "off" period of Q1, and we will establish some power and control equations.
We have seen that when Q1 turns "on," the current ramps up linearly in L1 to a peak value Ip = VdcTon/L1. Thus energy is stored in L1, and at the end of the "on" period, this stored energy will be
where E is in joules, L is in henries, and Ip is in amperes.
If the current through D1 (and hence L1) has fallen to zero before the next Q1 turn "on" action, all the energy stored in L1 (Eqn. 11) during the previous Q1 "on" period will have been delivered to the output load, and the circuit is said to be operating in the discontinuous mode.
The energy E in joules delivered to the load per cycle, divided by the period T in seconds, is the output power in watts. Thus if all the energy of Eqn. 11 is delivered to the load once per period T, the power to the load from L1 alone (assuming for the moment 100% efficiency) would be
4.3 The Continuous Mode Action in the Boost Regulator
As mentioned in the previous section, if the D1 current (the inductor current) falls to zero before the next turn "on" action, the circuit is said to operate in the discontinuous mode (see FIG. 10d).
However, if the current in D1 and L1 has not fallen to zero at the end of the "on" period, the inductor current will not be zero at the next Q1 turn "on" action. Hence the current in Q1 will have a front-end step as shown in FIG. 11. The current in the inductor cannot change instantaneously. Currents in Q1 and D1 will have the characteristic ramp-on-a-step waveshape as shown in FIG. 11.
The circuit is now said to be operating in the continuous mode because the inductor current does not reach zero during a cycle of operation.
FIG. 11 Typical current waveforms in Q1, D1, and L1 for a boost regulator operating in continuous mode. Note that inductor L1 has not had enough time to transfer all its energy to the load before the next Q1 turn "on" action.
Assuming the feedback loop maintains the output voltage constant, as Ro or Vdc decreases, the feedback loop increases the Q1 "on" period Ton to maintain the output voltage constant. As the load current increases, Ro or Vdc continues to decrease, a point is reached such that Ton is so large that the decaying current through L1 and D1 will not have fallen to zero before the next turn "on" action, and the action moves into the continuous mode as shown in Figures 10 and 11.
Now an error-amplifier circuit, which had successfully stabilized the loop while it was operating in the discontinuous mode, may not be able to keep the loop stable in the continuous mode and may oscillate. In traditional feedback-loop analysis, the continuous-mode boost regulator has a right-half-plane-zero in the transfer function.
(2) The only way to stabilize a loop with a right-half-plane-zero is to drastically reduce the error-amplifier bandwidth.
TIP: In simple terms, in the discontinuous mode, there is a short period when there is zero current in the inductor and zero current in D1. That is, there is a small time-gap between the energy transfer period (when Q1is "off" and D1 is conducting) and the energy storage period (when Q1 is "on" and D1 is not conducting). This time margin (dead time) is critical to the way the power system behaves and does not exist in the continuous mode.
It is very important to fully understand the difference between the two modes of operation, because in any switching topology that has a boost-type behavior, the effect will be evident. To better understand this, we will consider a transient load increase in a continuous mode boost topology and follow the sequence of events as the circuit responds to the load change.
Consider a continuous-mode buck system, running in steady-state conditions, with a stabilized output voltage and a load current that maintains the inductor in continuous conduction. We now apply a sudden increase in load current. The output voltage will tend to fall, and the control loop will increase the "on" period of Q1 to initiate an increase in current in L1. However, it takes several cycles before the current in L1 will increase very much (depending on the value of the inductor, the input voltage, and the actual increase in the Q1 "on" time).
It is important to notice that the immediate effect of increasing the "on" period is to decrease the "off" period (because the total period is fixed). Since D1 only conducts during the "off" period of Q1 (and this period is immediately reduced), the mean output current will initially decrease, rather than increase as was required. Hence we have a situation where we tried to increase the output current, but the immediate effect was to reduce the output current.
This will correct itself slowly as the current in the inductor increases over a few cycles.
From a control theory perspective, for a short time this effect introduces an additional 180 degr. of phase shift into the closed loop control system during the transient period when the L1 current is increasing. In terms of control theory this translates to a zero in the right half-plane of the transfer function; it is the cause of the right-half-plane-zero in the small signal transfer function.
Notice that the effect is related to the dynamic behavior of the power components and cannot be changed by the control circuit. In fact, a perfect high-gain fast-response control circuit would result in the "on" period going to the full pulse width on the first pulse, and there would be zero output current for a short period. Hence, the right-half-plane-zero cannot be eliminated by the loop compensation network. The only option is to slow down the rate of change of pulse width to allow the output to keep up without too much droop.
(In control theory parlance, the control loop must be rolled off at a frequency well below the right-half-plane-zero crossover frequency.) In the discontinuous mode the performance is quite different. The small time-gap margin allows the "on" period to increase without the need to reduce the "off" period (within the limits of the margin), so the problem is not present, providing the margin is large enough to accommodate the change in pulse width.
Be aware that in the continuous conduction mode, the right-half-plane-zero effect will be found in any switching converter (or combination of converters and transformers) that has a boost-type action in any part of the circuit. The flyback converter is a typical example of this. The mathematics of this effect will be found in Section 12 and reference 2.
4.4 Designing to Ensure Discontinuous Operation in the Boost Regulator
For the preceding reasons, the designer may prefer to ensure that the boost regulator remains fully within the discontinuous mode for the full range of operating conditions.
In FIG. 10d we see that the decaying D1 current just comes down to zero at the start of the next turn "on" action. This is the threshold between discontinuous and continuous mode operation.
This threshold is seen from Eqn. 16 to occur at certain combinations of Vdc, Ton, Ro ,L1, and T that result in the L1, D1 current just falling to zero prior to the next turn "on" action of Q1. It can be seen from FIG. 10a that any further decrease in Vdc or Ro (increase in load current) will force the circuit into the continuous mode such that oscillation can occur unless the error amplifier has been rolled off at a very low frequency.
To avoid this problem, we will see from Eqn. 16 that Ton must be selected so that when it is a maximum (which is when Vdc and Ro are at their minimum specified values) and the current in D1 has fallen back to zero, there is a usable working dead-time margin (Tdt) before Q1 turns "on" again.
At the same time, we must ensure that by the time the current in D1 returns to zero, the L1 core will have been restored to its previous starting place on its hysteresis loop, shown as B1 in FIG. 12. If the core is not fully restored to B1, then after many such cycles, the starting point will drift up the hysteresis loop and saturate the core. Since the impedance of a saturated core drops to its winding resistance only (because it cannot sustain voltage), the voltage at the transistor collector will suddenly move up to the supply volt age, and with negligible resistance in the path, the transistor will be destroyed.
In this example, to ensure that the circuit remains in the discontinuous mode, a dead-time Tdt of 20% of a full period will be provided.
Hence we must ensure that the sum of the maximum "on" time of Q1 plus the core reset time plus the dead time will equal a full period, as shown in FIG. 13. This will ensure that the stored current in L1 will have fallen to zero well before the next Q1 turn "on" action.
FIG. 13 Boost regulator waveforms in the discontinuous mode with 20% dead-time margin. For discontinuous-mode operation, the current in D1 (see FIG. 10) must have decayed to zero before the next turn "on" action.
To ensure this, the inductor L1 is chosen such that Ton(max) + Tr = 0.8T, leaving a dead time Tdt of 0.2T.
Now in Eqn. 16, with Vdc and Ro (maximum load current) specified, Ton is calculated from Eqn. 19 and k[= (Ton + Tr )/T)] = 0.8 from Eqn. 17.
Inductor L1 is fixed so the circuit is guaranteed not to enter the continuous mode. However, if the output load current is increased beyond its specified maximum value (Ro decreased below its specified minimum) or Vdc is decreased below its specified minimum, the feedback loop will attempt to increase Ton to keep Vo constant. This will eat into the dead time, Tdt, and move the circuit closer to continuous mode. To avoid this, we must limit the maximum "on" time or a maximum peak current must be provided.
TIP: A good method that accounts for all variables is to inhibit the turn "on" of Q1 until the inductor current reaches zero. For fixed-frequency operation this limits the load current. Alternatively it can be set up to provide variable frequency operation, which is often preferred. .
With L1 determined earlier from Eqn. 16, Vdc specified, and Ton calculated from Eqn. 19, the peak current in Q1 can be calculated from Eqn. 14, and a transistor selected to have adequate gain at Ip.
The boost regulator is frequently used at low power levels in non isolated applications due to the very low parts count. A typical application would be on a printed-circuit board where it is desired to step up a 5-V computer logic level supply to, say, 12 or 15 V for operational amplifiers.
Frequently at higher power levels in battery-supplied power supplies, as the battery discharges, its output voltage drops significantly.
Many systems whose prime power is a nominal 12- or 28-V battery will present problems when the battery voltage falls to about 9 or 22 V.
Boost regulators are frequently used in such applications to boost the voltages back up to the 12- and 28-Vlevel. Power requirements in such applications can be in the range 50 to 200 watts.
4.5 The Link Between the Boost Regulator and the Flyback Converter
The boost regulator has been treated in great detail because boost action appears in many converter combinations. For example, by re placing the inductor L1 with a transformer (more correctly a choke with an additional secondary winding), a very similar, valuable, and widely used topology, the flyback converter, is realized.
Like the boost, the flyback stores energy in its magnetics during the "on" period of the power device and transfers the energy to the output load during the "off" period.
Because the secondary windings can be isolated from the input, the outputs are not constrained to share a common return line. Also by using multiple secondaries, a multiple output power supply is possible. The outputs may be higher or lower voltage than the input, and may be common or isolated as required.
The problems of discontinuous or continuous operation and the design relationships and procedures for the flyback are similar to those of the boost regulator and will be discussed in more detail in Section 4.
5. The Polarity Inverting Boost Regulator
5.1 Basic Operation
FIG. 14 shows a different arrangement of the boost regulator that provides polarity inversion. It uses the same basic principle as the previous boost regulator in that energy is stored in the inductor during the "on" period of Q1, which is then transferred to the output load and Co in the "off" period of Q1.
Comparing Figures 14 and 10, it will be seen that the transistor and inductor have changed places. In the reverse polarity inverter, the transistor is above the inductor rather than below it as it was in the boost circuit. Also the rectifying diode has been reversed.
When Q1 turns "on," diode D1 is reverse biased because its cathode is at Vdc (assuming to a close approximation that the voltage drop across Q1 is zero). Also, assuming steady-state conditions, such that Co has charged down to some negative voltage, then D1 remains re verse biased throughout the Q1 "on" period. A fixed-voltage Vdc will be impressed across the inductor Lo , and the current in it ramps up linearly at a rate di/dt = Vdc/Lo .
After an "on" period Ton, the current in Lo will have reached Ip = VdcTon/Lo , and the energy stored in Lo (in joules) is E =.5Lo I 2 p. When Q1 turns "off," the voltage polarity across Lo reverses in an attempt to maintain its current constant. Thus at the instant of turn "off," the same inductor current Ip (which was flowing through Q1 before it turned "off") now continues to flow down through Lo to common, pulling the current through D1 from Co . This current charges the top end of Co to a negative voltage.
After a number of cycles, when the required output voltage is developed, the error amplifier adjusts the Q1 "on" period Ton so that the sampled output voltage Vo R2/(R1+ R2) is equal to the reference voltage Vref. Further, if all the energy stored in Lo is delivered to the load before the next Q1 turn "on" action (that is, ID1 has fallen to zero), then the circuit operates in the discontinuous mode, and the power delivered to the load will be
It should be noted that unlike the case of the boost regulator, when Q1 turns "off," the inductor current does not flow from the supply source (see Eqn. 13).Hence the only power to the load is that given by Eqn. 20. Thus assuming 100% efficiency, the output power would be
5.2 Design Relations in the Polarity Inverting Boost Regulator
As in the previous boost circuit, it is desirable to keep the circuit operating in the discontinuous mode by ensuring that the current stored in Lo during the Q1 maximum "on" period has decayed to zero at the end of the "off" period Tr . To ensure this action, we will provide a dead time Tdt margin of 0.2T before the next Q1 turn "on" action.
Thus if Ton + Tr + Tdt = T, then for Tdt = 0.2T we obtain
Ton + Tr = 0.8T (eqn. 23)
In addition, as in the boost regulator, the "on" volt-second product must equal the reset volt-second product to prevent the core from saturating. Since (as can be seen from Eqn. 22) the maximum Ton occurs for minimum Vdc and minimum Ro (maximum current), it follows that
VdcTon = Vo Tr (eqn. 24)
Thus both Eqs. 23 and 24 have two unknowns: Ton and Tr . This
fixes Ton at
Now, with Ton calculated from Eqn. 25 and Vdc, Ro ,Vo , and T specified, Eqn. 22 defines Lo such that Ip = VdcTon/Lo , and transistor Q1 is selected to have adequate gain at Ip.