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In the three switching regulator topologies discussed in the previous section, the output returns were all common with the input returns, and multiple outputs were not possible (except for the special case discussed in Section 3.8).
In this section we look at some of the most widely used fully isolated switching regulator topologies. These topologies-the push pull, single-ended forward converter, and the double-ended and inter leaved forward converters-are similar, so we consider them a single family. All these topologies deliver their power to the loads via a high frequency transformer; hence outputs may be DC-isolated from the input, and multiple outputs are possible.
2. The Push-Pull Topology
2.1 Basic Operation (With Master/ Slave Outputs)
A push-pull topology is shown in FIG. 1. It consists of a trans former T1 with multiple secondaries. Each secondary delivers a pair of 180 degr. out-of-phase square-wave power pulses whose amplitude is fixed by the input voltage and the number of primary and secondary turns.
The pulse widths for all secondaries are identical, as determined by the control circuit and the negative-feedback loop around the master output. The control circuit is similar to the buck and boost regulators shown previously in Figures 4 and 10, except that two equal adjustable pulse-width, 180-degrees-out-of-phase pulses drive the bases of Q1, Q2. The additional secondaries Ns1, Ns2 are referred to as slaves.
Transistor base drives at turn "on" are sufficient to bring the switched end of each half primary down to Vce(sat) , typically about 1 V, over the full specified current range. Hence as each transistor turns "on," it applies a square-voltage pulse to its half primary of magnitude Vdc - 1.
On the secondary side of the transformer, there will be flat-topped square waves of amplitude (Vdc - 1)(Ns /Np) - Vd with a duration To , where Vd is an output rectifier forward drop, taken as 1 V for a conventional fast-recovery diode, and 0.5 V for a Schottky diode. The output pulses at the rectifier cathodes have a duty cycle of 2Ton/T because there are two pulses per period.
Thus the waveforms at the inputs to the LC filters shown in FIG. 1 are very much like that at the input to the buck regulator LC filter of Figure 1.4,which has a flat-topped amplitude and adjustable width.
The LC filters of FIG. 1 serve the same purpose as that of Figure 4. They provide a DC output that is the average of the square wave voltage at the input of the filter. The analysis of the inductor and capacitor functions proceeds exactly as for the buck regulator, and the method of calculating their magnitudes is exactly the same as follows.
The DC or average voltage at the Vm output in FIG. 2 (assuming D1, D2 are 0.5-V forward-drop Schottky diodes) will be ...
The waveforms at the Vm output rectifiers are shown in FIG. 2.
If the negative-feedback loop is closed around Vm as shown in Figure 2.1, Ton and Vm will be regulated against DC input voltage and load
Vm = [(Vdc - 1)(Nm/Np) - 0.5](2Ton/T)
As Vdc varies, the negative-feedback loop corrects Ton in the direction to keep Vm constant.
current changes. Although load current does not appear in Eqn. 1, a current change will cause Vm to change, that change will be sensed by the error amplifier, and Ton will be altered to correct it. Providing the current in L1 (see FIG. 1) does not go discontinuous, changes in Ton will be small, and the absolute value of Ton will be given by Eqn. 1 for any turns ratio Nm/Np, input voltage Vdc, and period T.
For the slave secondaries, the voltages at the cathodes of the rectifying diodes are fixed by the number of secondary turns, and the Ton duration of the square waves is the same as defined by the master feedback loop. Thus the slave output voltages with normal diodes will be
2.2 Slave Line-Load Regulation
It can be seen from Eqs. 1, 2, and 3 that the slaves are regulated against Vdc input changes by the negative-feedback loop that keeps Vm constant, in accordance with Eqn. 1. The same equation, Vm = (Vdc - 1)Ton also appears in Eqs. 2 and 3, and thus Vs1,Vs2 are also kept constant as Vdc changes.
Notice that if load current in the master (Vm) changes, the drops across its rectifying diodes and winding resistance will change slightly.
Thus the negative-feedback loop will correct for Vm load change effects and alter Ton to keep Vm constant.
For the slave outputs, Ton will now change without corresponding changes in Vdc, and from Eqs. 2 and 3, it can be seen that changes in Vs1, Vs2 will result. Such changes in the slave output voltages due to changes in the master output current are referred to as cross regulation.
Slave output voltages will also change as a result of changes in their own output currents. In a similar way slave current changes will cause voltage drop changes in their rectifying diodes and winding resistances, lowering the peak voltages slightly. These changes are not corrected by the main feedback loop, which senses only Vm.
However, providing the currents in the slave output inductors L2, L3, and especially in the master inductor L1 do not go discontinuous, slave output voltages can be depended on to vary within only ± 5 to ± 8%.
TIP Much better cross regulation can be obtained by using coupled output inductors (where all outputs share a common inductor core).
2.3 Slave Output Voltage Tolerance
Although changes in slave output voltages are relatively small, the absolute values of output voltage are not accurately adjustable. As seen in Eqs. 2 and 3, they are fixed by Ton and their corresponding secondary turns Ns1, Ns2. But Ton is nearly constant, defined by the feedback loop to keep the master voltage constant. Further, since the turns can be changed only by integral numbers, the absolute value of slave output voltage is not finely settable. The change in secondary voltage for a single turn change in Ns is given by Vm. Ton/Np.
Inmost cases, the absolute values of slave output voltage are not too important. Slaves usually drive operational amplifiers or motors, and most often these can tolerate DC voltages within about 2Vof a desired value. If the absolute magnitude is important, the output voltage is usually designed to be higher than required and brought down to a desired exact value with a linear or buck regulator. Because a slave output is semi-regulated, a linear regulator is reasonably efficient.
2.4 Master Output Inductor Minimum Current Limitations
The selection of the output inductor for a buck regulator was discussed in Section 3.6. It was mentioned that at the average current in which the step at the front of the inductor current waveform has fallen to zero (see Figures 6a and 6b), the inductor is said to run dry or to go discontinuous. Below this average current, the feedback loop maintains the buck regulator's output voltage constant by reducing the "on" period; this results in reduction of slave output voltages.
In Figure 6a, however, it can be seen that at currents above going discontinuous, the "on" time is very nearly constant over large output current changes. Below run-dry, the "on" time changes drastically.
In the buck regulator this does not pose a major problem because only one output is involved and the feedback loop keeps this output voltage constant. But in the push-pull width-modulated converter with a master and some slaves, the slave output voltages are directly proportional to the master "on" time, as shown by Eqs. 2 and 3.
Hence, when slaves are involved it is important that the average master output inductor current not be permitted to go discontinuous above its specified minimum. If the master minimum output current is specified at one-tenth its nominal value for example, a minimum output inductor value must be selected from Eqn. 8. The slave out put voltages will vary within about 5% above the master inductor discontinuous current. Below this critical current, the feedback loop will keep the master output voltage constant by decreasing Ton significantly, followed by the slave output voltages.
Further, the slave outputs must not be permitted to go discontinuous above their own specified minimum currents. Slave output inductors should also be selected from Eqn. 8. Clearly, larger minimum currents imply smaller inductors.
TIP This problem is also eliminated by using coupled output inductors.
1 . The push-pull converter is one of the oldest topologies and is still popular. It can provide multiple outputs whose returns are DC-isolated from input ground and from one another. Output volt ages can be higher or lower than the input voltage. The master is regulated against line and load variations. The slaves are equally well regulated against line changes and can be within about 5% for load changes as long as output inductors are not permitted to go discontinuous.
2.5 Flux Imbalance in the Push-Pull Topology (Staircase Saturation Effects)
The designer needs to be aware of a rather subtle failure mode in push pull converters, known as staircase saturation, caused by a possible flux imbalance in the transformer core.
This effect can best be understood by examination of a typical hysteresis loop of a ferrite core material used in the power transformer as shown in FIG. 3.
In normal operation, core flux excursions are between levels such as B1 and B2 gauss in FIG. 3. It is important to stay on the linear part of the hysteresis loop below about ± 2000 G. At frequencies up to 25 kHz or so, core losses are low and these maximum excursions are permissible. As discussed in Section 220.127.116.11, however, core losses go up rapidly with frequency, and above 100 kHz conservative design limits peak flux density to 1200 or even 800 G.
It can be seen in FIG. 1 that when Q1 is "on," the no-dot end of Np1 is positive with respect to the dot end, and the core moves up the hysteresis loop-say, from B1 toward B2. The actual amount it moves up is proportional to the product of the voltage across Np1 and Q1 "on" time (from Faraday's law; see Eqn. 18). When Q1 turns "off" and Q2 turns "on," the dot end of Np2 is positive with respect to the no-dot end, and the core moves back down from B2 toward B1. The actual amount it moves down is proportional to the voltage across Np2 and the Q2 "on" time.
FIG. 3 Hysteresis loop of a typical ferrite core material (Ferroxcube 3C8). Flux excursions are generally limited to ± 2000 G up to about 30 kHz by requirement to stay on the linear part of the loop. At higher frequencies of 100 to 300 kHz, peak flux excursions must be reduced to about ± 1200 or ± 800 G because of core losses. Material 3C8 is a ferrite from Ferroxcube Corporation. Other materials from this or other manufacturers are very similar, differing mainly in core losses and Curie temperature.
Further, if the volt-second product across Np1 while Q1 is "on" is equal to the volt-second product across Np2 while Q2 is "on", after one complete period the core will have moved up from B1 to B2 and returned exactly to B1. But if those volt-second products differ by only a few percent and the core has not returned to its exact starting point each cycle, after a number of periods the core will "walk" or "staircase" up or down the hysteresis loop into saturation. In saturation, of course, the core cannot sustain voltage, and the next time a transistor turns "on," it will be destroyed by high current and high voltage.
A number of factors can cause the "on" volt-second product to be different from the "off" or reset volt-second product. The Q1 and Q2 collector voltages and "on" times may not be exactly equal even if their base drive "on" times are equal. If Q1, Q2 are bipolar transistors, they have "storage" times that effectively keep the collector "on" after base drive is removed. Storage times can range from 0.3 to 6 µs and have large production spreads. They are also temperature-dependent, increasing significantly as temperature increases. Even if Q1 and Q2 have equal storage times, they may become unequal if located on a heat sink such that they operate at different temperatures.
Hence if one transistor has a volt-second product only slightly larger than the other, it will start the core progressively drifting off-center toward saturation with each cycle. This will cause one transistor to draw slightly more current than the other as the core moves onto the curved part of the hysteresis loop (see FIG. 3). As a result, the core magnetizing current on that half-period starts to become a significant part of the load current. The transistor that draws more current will now run slightly warmer, increasing its storage time. With a longer storage time in that transistor, the volt-second product it applies to the core in its "on" half period increases, the current in that half period increases, and storage time in that transistor increases still further.
Thus a runaway condition arises that quickly drives the core into saturation and destroys the transistor.
The "on" volt-second products of Q1 and Q2 also can differ because of their initially unequal "on" or Vce(sat) voltages, which have a significant production spread. As described earlier, with bipolar transistors, any initial difference in "on" voltage is magnified because the "on" voltage of bipolars decreases as temperature increases.
If Q1, Q2 are MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), the flux-imbalance problem is much less serious. To start with, MOSFETs have no storage time, and with equal input "on" (gate) times, output (drain) times are equal and, importantly, the "on" volt age of a MOSFET transistor increases as temperature increases. Thus the runaway condition described earlier is reversed, providing some compensation. If there were any initial volt-second inequality, one FET current would be greater as the core started moving up the curved part of the hysteresis loop. The FET with the larger current would run warmer, and its "on" voltage would increase and rob voltage from its half primary. This would decrease the volt-second product in that half period and bring the transistor current back down, providing some compensation.
2.6 Indications of Flux Imbalance
The earlier description might imply that any slight imbalance in volt second product between half cycles causes certain failure, but this is not necessarily so. A push-pull converter can continue to operate reliably with a small amount of flux imbalance without immediately saturating its core and destroying its transistors. Many low power, low voltage push-pull converter designs run quite reliably in spite of the apparent problems.
Notice that with a small volt-second imbalance, if there were not an inherent corrective mechanism, core saturation and transistor failure would always occur after a few switching cycles. Thus, if there were an initial volt-second imbalance of say 0.01% (which would be practically impossible to achieve), it would take only 10,000 cycles until the core would move from a low starting point of B1 (see FIG. 3) to a saturating point of B2, and the transistors would probably be destroyed before that.
One corrective mechanism, that may permit the converter to survive, is the primary winding resistance. If there is an initial volt-second imbalance, the transistor taking more current produces a larger voltage drop across its half primary winding resistance. That voltage drop robs volt-seconds from the winding and tends to restore the volt second balance.
Thus the converter can remain in an unbalanced state without immediately going into runaway and completely saturating the core. An indication of where the core is working on the hysteresis loop can be obtained by placing a current probe in the transformer center tap as shown in Figure 4d.
The waveform indicating volt-second balance is shown in FIG. 4a, where alternate current peaks are equal. Primary load current pulses have the characteristic shape of a ramp on a step just as for the buck regulator shown here. They have this shape because all the secondaries have output LC filters that generate such waveshapes as described in Section 3.2.
The primary load current is the sum of all the secondary currents reflected into the primary by their respective turn ratios. However, the total primary current is the sum of these secondary currents plus the primary magnetizing current. The magnetizing current is the cur rent drawn by the magnetizing inductance, which is the inductance seen looking into the primary with all secondaries open-circuited.
This inductance is always present and effectively is in parallel with the primary winding. This current is added to the secondary currents reflected into the primary as in FIG. 4e.
The waveshape of the total primary current is then the sum of the ramp-on-a-step reflected load currents and the magnetizing current.
But providing the core is working in the linear area of the B/H loop, the magnetizing current will be a linear ramp starting from zero current each cycle.
When a transistor turns "on," it applies a step of voltage of approximately Vdc - 1 across the magnetizing inductance L pm. Magnetizing current then ramps up linearly at a rate
dI/dt = (Vdc - 1)/L pm (eqn 4)
and for the transistor "on" time of Ton it reaches a peak of
Core is not yet on curved part of hysteresis loop. (c) Unequal volt-second product. Upward concavity indicates dangerous situation. Core is far up on curved part of hysteresis loop. (d) Adding a diode in series with one side of primary to test how serious a volt-second inequality exists. (e) Total primary current is the sum of the ramp-on-a-step reflected secondary load currents plus the linear ramp of magnetizing current.
The magnetizing current Ipm is kept small compared with the sum of the load currents reflected into the primary by ensuring that L pm in Eqn. 5 is large. By design, the peak magnetizing current should be no greater than 10% of the primary load current.
When added to the ramp-on-a-step load current, the ramp of magnetizing current is small, and it simply increases the slope of the latter slightly. Also, if the volt-seconds are equal on alternate half cycles, the peak currents will also be equal on each half cycle as in FIG. 4a, because operation is centered around the origin of the hysteresis loop of Figure 3.
However, if the volt-second products on alternate half cycles are unequal, core operation is not centered on the origin of the hysteresis loop. Since the horizontal scale (H oersteds) is proportional to magnetizing current, this shows up as a DC current bias as in FIG. 4b, making alternate current pulses unequal in amplitude.
As long as the DC bias does not drive the core up the hysteresis loop appreciably, the slope of the ramp still remains linear (Fig. 4b) and operation is still reasonably safe. Primary wiring resistance may keep the core from moving further up into saturation.
But if there is a large inequality in volt-seconds on alternate half cycles, the core is biased closer toward saturation and enters the curved part of the hysteresis loop. Now the magnetizing inductance, which is proportional to the slope of the hysteresis loop, decreases and magnetizing current increases significantly. This shows up as an upward concavity in the current slope in FIG. 4c.
This is a dangerous and imminent failure situation. Now even a small temperature increase can bring on the runaway scenario described earlier. The core will be driven hard into saturation and destroy the power transistor. A push-pull converter design should certainly not be considered safe if current pulses in the primary center tap show any upward concavity in their ramps. Even linear ramps as in FIG. 4b with anything greater than 20% inequality in peak currents are unsafe and should not be accepted.
Note: A more damaging effect can occur if there is a sudden transient load change, because the extra current can take the core immediately into saturation. .
2.7 Testing for Flux Imbalance
A simple test to determine how close to a dangerous flux-imbalance situation a push-pull converter may be operating is shown in FIG. 4d. Here a silicon diode with about 1V forward drop is placed in series with one half of the transformer primary. Now in the "on" state, that half with the diode in series has 1V less voltage across it than the other half, and there is an artificially produced volt-second unbalance. The center tap waveform will then look like either Figure 4b or 4c. The current ramp corresponding to the side that does not have the diode will have the larger volt-second product and the larger peak current. By switching the diode to the other side, the larger peak current will be seen to switch to the opposite transformer half primary.
Now the closeness of the circuit to the upward concave situation of FIG. 4c can be determined. If one series diode can make a current ramp go concave, the circuit is too close to imminent failure. Placing two series diodes on one side will give an indication of how much margin there is.
It should be noted that primary magnetizing current contributes no power to the secondaries. It will not appear in the secondaries. It simply swings the magnetic core across the hysteresis loop.
In FIG. 3, the magnetizing force H in oersteds (Oe) is related to the current by the fundamental magnetic relation
where Np is the number of primary turns Im is the magnetizing current in amperes lm is the magnetic path length in cm.
2.8 Coping with Flux Imbalance
Flux imbalance can become a major problem at high voltages and high powers. There are a number of ways to circumvent the problem, but most involve increased cost or component count. Some schemes to combat flux imbalance are described in the following subsections.
2.8.1 Gapping the Core
Flux imbalance becomes serious when the core moves out onto the curved part of the hysteresis loop (see FIG. 3) and magnetizing current starts increasing exponentially as in FIG. 4c. This effect can be reduced by moving the curved part of the hysteresis loop to a higher current by tilting the hysteresis loop. The core can then tolerate a larger DC current bias or volt-second product inequality.
An air gap introduced into the magnetic path of the core has the effect shown in FIG. 5. It tilts the slope of the hysteresis loop.
An air gap of 2 to 4 mils (thousandths of an inch) brings the curved portion of the loop much further away from the origin so that the core can accept a reasonably large offset in H (current imbalance). This can help at higher power levels. It has the disadvantage of reducing the inductance so that the critical current must be larger to prevent discontinuous-mode operation.
The air gap for a prototype EE or cup core is easily effected with plastic shims in the center and outer legs. Since the flux passes through the center leg and returns through the outer legs, the total gap is twice the shim thickness. In a production transformer, it is not very much more expensive to have the center leg ground down to twice the shim thickness. This will achieve pretty much the same effect as shims in the center and outer legs, but is preferable as the gap will not change with changes in the thickness of the plastic and results in less magnetic radiation and hence reduced RFI interference.
2.8.2 Adding Primary Resistance
It was pointed out in Section 2.6 that primary wiring resistance keeps the core from being driven rapidly into saturation if there is a volt second inequality. If there is such an inequality, the half primary with the larger volt-second product draws a larger peak current. That larger current causes a larger voltage drop across the wiring resistance and robs volt-seconds from that half primary, restoring the current balance.
This effect can be augmented by adding additional resistance in series with both primary halves. The added resistors can be located in either the collectors or emitters of the power transistors. The value is best determined empirically by observing the current pulses in the transformer center tap. The required resistors are usually under 0.25 ohm.
They will, of course, increase power loss and reduce efficiency.
2.8.3 Matching Power Transistors
Since volt-second inequality arises mainly from an inequality in storage time or voltage in the power transistors, if those parameters are matched, it adds confidence that together with the earlier two "fixes" there will be no problem with flux imbalance.
This is not a good solution and would be an expensive fix as it is quite expensive to match transistors in two parameters. To do such matching requires a specialized test setup that would not be available if field replacements become necessary.
It also must be ascertained that if the matching is done at certain load currents and temperature, the matching still holds when these vary. Further, a storage time match is difficult to make credible, as it depends strongly on forward and reverse base input currents in the bipolar transistors. Generally any matching is done by matching Vce and Vbe (the "on" collector-to-emitter and base-to-emitter voltages) at the maximum operating current. Hence matching is not a viable solution for high-volume commercial supplies.
2.8.4 Using MOSFET Power Transistors
Since most of the volt-second inequality arises from storage time inequality between the two bipolar power transistors, the problem largely disappears if MOSFETs are used, because they have no storage time.
There is an added advantage, as the "on" voltage of a MOSFET transistor increases with temperature. Thus if one half primary tends to take a large current, its transistor runs some what warmer and its "on" voltage increases and steals voltage from the winding. This reduces the volt-second product on that side and tends to restore balance. This, of course, is qualitatively in the right direction, which is helpful but cannot be depended on to solve the flux-imbalance problem reliably at all power levels and with a worst-case combination.
However, with power MOSFETs at power levels under 100 W and low input voltages (as inmost DC/DC converter applications), push pull converters can be and are built with a high degree of confidence.
2.8.5 Using Current-Mode Topology
By far the best solution to the flux-imbalance problem is to use current mode control. This completely and reliably solves the flux-imbalance problem; also it has significant additional advantages of its own.
In conventional push-pull, there is always a residual concern that despite all the fixes, a flux-imbalance problem will arise in some worst-case situation and a transistor will be destroyed. Current-mode topology solves this problem by monitoring the current in each of the push-pull transistors on a pulse-by-pulse basis. The control circuit then forces alternate current pulses to have equal amplitude, maintaining the working point very near the center of the B/H loop.
Details of current-mode topology will be discussed in Section 5.
2.9 Power Transformer Design Relationships
Note: The design of wound components is a specialized subject and is covered in more detail in Section 7. The correct design of transformers, inductors, and chokes is essential for optimum performance of the equipment. The engineer who takes the time to become fully competent in this area will get much better results, so the reader is urged to study Section 7 before proceeding with any real designs.
In the following section we show an iterative method for selecting the core size and winding parameters. It serves as a good example of the rather lengthy process required if this method is used.
The reader will do well to study this process, which shows the interaction between the various parameters. However, in practice, optimum designs normally start by defining the maximum permitted temperature rise (typically 30 degr. C), and one of the nomogram-assisted methods or computer programs would be used to provide a much faster solution with a defined result, avoiding the tedious iterative procedure.
2.9.1 Core Selection
The design of a transformer starts with the initial selection of a core to satisfy the desired total output power. The available output power from a particular core depends on the operating frequency, the operating flux density swing (B1 and B2 in FIG. 3), the core's area Ae , the bobbin winding window area Ab , and the current density in each winding.
Decisions on each of these parameters are interrelated, and choices are made to minimize the transformer size and its temperature rise.
In the magnetics section of Section 7 an equation is derived showing a recommended output power for a given core as a function of the parameters mentioned earlier.
The equation can be used in a set of iterative calculations, first making a tentative selection of a specific core, peak flux density, and operating frequency, and calculating the available output power. Then if the available power is insufficient, a larger-sized core is selected and the calculations repeated until a core with the required output power is found.
This is a long and cumbersome procedure; instead the equation is turned into a set of charts that permit a core and operating frequency to be selected at a glance for any desired output power. Such equations and charts will be found for most of the commonly used topologies in Section 7.
We will assume that these charts will be used to select a specific core so that the area Ae is known. The rest of the transformer design involves calculation of the number of turns on the primary and secondaries, selection of wire sizes, calculation of core and copper losses, and finally the calculation of transformer temperature rise.
The optimum arrangement of the various layers of wire on the core bobbin is important in improving coupling between the windings and in reducing copper losses due to "skin" and "proximity" effects.
Winding arrangements, skin, and proximity effects will be discussed in Section 7.
For this example, the design will proceed using the core chosen from the selection charts described earlier, providing a known value of the core area Ae .
2.9.2 Maximum Power Transistor On-Time Selection
Equation 1 has shown that the converter keeps the output voltage Vm constant by increasing Ton as Vdc decreases. Thus the maximum "on" time Ton occurs at the minimum specified DC input voltage Vdc .
But in this type of converter the maximum "on" time must not exceed half the switching period T. If it were to do so, the reset volt-second product would be less than the set volt-second product, and after a very few cycles, the core would drift into saturation and destroy a power transistor.
Moreover, because of the inevitable storage time in bipolar transistors, the base drive "on" time cannot be as large as a full half period, as the storage time would cause an overlap with the opposite transistor.
This would result in immediate failure, because the two power transistors would effectively short out the winding. Each transistor would take large currents at the full supply voltage and would rapidly be destroyed.
Thus, to ensure that the core will always be reset within one period and eliminate any possibility of simultaneous conduction, whenever the DC input voltage is at its minimum Vdc and the feedback loop is trying to increase Ton to maintain Vm constant, the maximum "on" time will be constrained by some kind of a clamp so as to never be more than 80% of a half period. Then in Eqn. 1, for the specified Vdc,T and for Ton = 0.8T/2, the ratio Nm/Np will be fixed to yield the desired output Vm.
TIP: Modern drive and control ICs provide adjustable (so-called) "dead time" to prevent power device overlap. In some designs, dynamic methods are provided such that the state of conduction of the power devices is monitored and the drive signal is delayed until the previous active power device has turned fully "off," before the next is allowed to turn "on." This allows the full range of duty cycle to be utilized while completely eliminating any possibility of overlap.
2.9.3 Primary Turns Selection
The number of primary turns is determined by Faraday's law(see Eqn. 17). From it Np is fixed by the minimum voltage across the primary (Vdc - 1) and the maximum "on" time, which, as earlier, is to be no more than 0.8T/2. Then ...
Since Ae in Eqn. 7 is fixed by the selected core, Vdc and T are specified and the number of primary turns is fixed as soon as dB (the desired flux change in 0.8T/2) is decided on. This decision is made as follows.
TIP The reader may prefer to use a dimensionally modified version of Faraday's law that provides turns directly as follows:
Where N = turns V = voltage across the winding (Vdc) Ton = maximum "on" period, microseconds
_B = flux density swing, teslas (1 tesla = 10,000 gauss)
Ae = effective core area, mm^2
For all magnetic calculations, I prefer to work in the preceding modified SI units, as these yield immediate solutions, avoiding the unwieldy exponents, thus reducing errors.
2.9.4 Maximum Flux Change (Flux Density Swing) Selection
From Eqn. 7, it is seen that the number of primary turns is inversely proportional to dB, the flux swing. It would seem desirable to maximize dB so as to minimize Np, since fewer turns would mean that a larger wire size could be used, resulting in higher permissible currents and more output from a given core. Also, fewer turns would result in a less expensive transformer and lower stray parasitic capacities.
From the hysteresis loop of FIG. 3, however, it is seen that in ferrite cores, the loop enters the curved portion above ±2000 G. It is desirable to stay below this point, where the magnetizing current starts increasing rapidly. So initially a good choice would appear to be ±2000 G (0.2 tesla). But we must also consider core losses.
Ferrite core losses increase at about the 2.7th power of the peak flux density and at about the 1.6th power of the operating frequency.
Hence, up to about 50 kHz, core losses do not prohibit operation to ± 2000 G, and it may appear desirable to operate at that flux level.
However, to prevent core saturation under transient conditions, it is better to provide a wider margin. We will see shortly that it is preferable to restrict operation to ± 1600 G even at frequencies where core losses are not prohibitive. Faraday's law solved for the flux change dB is:
Equation 2.8 says that if Np is chosen for a given dB-say, from -2000 to +2000 G, or a dB of 4000 G, then as long as the product of (Vdc - 1)(Ton) is constant, dB will be constant at 4000 G. Further, if the feedback loop is working and keeping the output voltage Vm constant, Eqn. 1 says that (Vdc - 1)(Ton) is constant and dB will truly remain constant. So providing the feedback loop always ensures that whenever Vdc is a minimum, that Ton is at a maximum, then Ton and Vdc can never be simultaneously maximum.
However, in some transient or fault conditions, if Ton has been at maximum for a single, or possibly even a few cycles, and Vdc had a transient step to 50% above its normal value, the feedback loop may fail to reduce the "on" time rapidly enough (as normally required by Eqn. 1), and there may exist a short period when Vdc and Ton would be maximum at the same time. In this event, Equation 8 shows that dB would be 1.5(4000) or 6000 G.
Then if the core had started from the -2000-G point, at the end of that "on" time the core would have been driven 6000 G above that, or to +4000 G. The hysteresis loop (see FIG. 3) shows that at temperatures somewhat above 25 degree C, it would be deep in saturation and could not support the applied voltage. The transistor would be subject to high current and high voltage and would rapidly fail.
It will be seen in the feedback analysis section of Section 12 that the error amplifier has a delay in its response time, because its bandwidth is limited to stabilize the feedback loop. Hence, it is always possible for both the input voltage and "on" time to be maximum for a transient period due to the inevitable delay in the response of the error amplifier, although the error amplifier will eventually correct the "on" time so as to keep the product (Vdc - 1)(Ton) constant in accordance with Eq. 1. If the core is subjected to maximum input voltage and maximum "on" time as a result of error-amplifier delay, even for a single cycle, it may saturate the core and destroy a transistor.
However if Np in Eqn. 8 is chosen to yield dB of 3200 G at Vdc and Ton, the design is safer and can tolerate a 50% transient step in input voltage. With dB = 3200 G, if the error amplifier is too slow to correct the "on" time, the transformer dB will be 1.5(3200) or 4800 G; and if the core started from its normal minimum flux of -1600 G, it will be driven up to only -1600 + 4800 or +3200 G. The hysteresis loop of FIG. 3 shows that the core can tolerate that even at 100 degr. C.
Thus the number of primary turns is selected from Eqn. 7 for dB = 3200 G even at lower frequencies where a large flux may not cause excessive core losses. Above 50 kHz, the core losses increase rapidly and force a lower flux density selection. At 100 to 200 kHz, the peak flux density may be limited to 1200 or even 800 G to achieve an acceptably low core temperature rise.
2.9.5 Secondary Turns Selection
The turns for the main and slave outputs are calculated from Eqs. 1, 2, and 3 in accordance with the specified, or calculated, voltage requirements. We see that the input voltage Vdc and T have been specified. The maximum "on" time Ton has been arbitrarily set at 0.8T/2, and Np has been calculated from Faraday's law (see Eqn. 7) for the known Ae for the selected core. Flux swing dB has been set at 3200Gfor frequencies under 50 kHz and to minimize core losses. Lower values will be used at higher frequencies as discussed earlier.
2.10 Primary, Secondary Peak and rms Currents
In this example, wire sizes will be selected on the basis of a conservative operating current density. Current density is given in terms of rms current in amps per circular mil* of wire cross-sectional area.
Hence, before we can start selecting wire sizes for any winding, we require a knowledge of the rms currents in each winding.
2.10.1 Primary Peak Current Calculation
Current drawn from the DC input source Vdc may be monitored in the transformer center tap and has the waveform shown in Figures 1b and 1d. The pulses have the characteristic ramp-on-a-step wave shape because the secondaries all have output LC filters as discussed in Section 3.2. The primary current is simply the sum of all the secondary ramp-on-a-step currents reflected into the primary by their turns ratios, plus the magnetizing current.
As discussed in Section 2.9.2, at minimum Vdc input voltage, the transistor "on" times will be 80%of a half period. Further, since there is one pulse for each half period, the duty cycle of the pulses in FIG. 1 is 0.8 at Vdc. To simplify calculation, the pulses in the figure are assumed to have an equivalent flat-topped waveshape whose amplitude Ipft is the value of the current at the center of the ramp.
Then the input power at Vdc is that voltage times the average cur rent, which is 0.8Ipft, and assuming 80% efficiency (which is usually achievable up to 200 kHz), Po = 0.8Pin or ...
This is a useful relation, as it gives the equivalent flat-topped primary current pulse amplitude in terms of what is known-the output power and the specified minimum DC input voltage. It allows selection of a primary wire size from the calculated primary rms current. It also allows a transistor with an adequate current rating to be selected.
2.10.2 Primary rms Current Calculation and Wire Size Selection
Each half primary carries only one of the Ipft pulses per period, and hence its duty cycle is (0.8T/2)/T or 0.4. It is well known that the rms value of a flat-topped pulse of amplitude Ipft at a duty cycle D is ...
This gives the rms current in each half primary in terms of the known parameters: output power and the specified minimum DC input voltage.
A conservative practice in transformer design is to operate the windings at a current density of 500 circular mils per rms ampere.
There is nothing absolute about this; current densities of 300 circular mils per rms ampere are frequently used for windings with only a few turns. As a general rule, however, densities greater than 300 circular mils per rms ampere should be avoided, as that will cause excessive copper losses and temperature rise.
Thus at 500 circular mils per rms ampere, the required number of circular mils for the half primaries is ...
Notice that this is also in terms of known values-output power and specified minimum DC input voltage. Proper wire size can then be chosen from wire tables at the circular mils given by Eqn. 12.
2.10.3 Secondary Peak, rms Current, and Wire Size Calculation
Currents in each half secondary are shown in FIG. 6. Note the ledge at the end of the transistor "on" time. This ledge of current exists because there is no free-wheeling diode D1 at the input to the filter inductor as in the buck regulator of Figure 4. In the buck, the free wheeling diode was essential as a return path for inductor current when the transistor turned off. When the transistor turned off, the polarity across the output inductor reversed, and its input end would have gone disastrously negative if it had not been caught by the free wheeling diode at about 1 V below ground. Inductor current then continued to flow through the free-wheeling diode D1 of Figure 4e.
This problem does not exist in the rectifier circuit shown in Figure 6.
In the push-pull output rectifier stage, the function of the free wheeling diode is performed by the output rectifier diodes D1 and D2. When either transistor turns "off," the input end of the inductor tries to go negative. As soon as it goes about one diode drop below ground, both rectifiers conduct, each drawing roughly half the total current the inductor had been drawing just prior to turn "off" (see Figures 6d and 6e). Since the impedance of each half secondary is small, there is negligible drop across them, and the rectifier diode cathodes are caught at about 1 V below ground.
Thus if half-secondary rms currents are to be calculated exactly, the ledge currents during the 20%dead time should be taken into account.
However, in this example it can be seen that they are only about half the peak inductor current and have a duty cycle of (0.4T/2)/T or 0.2.
With such small amplitudes and duty cycle they can be ignored in this example. Each half secondary can then be considered to have the characteristic ramp-on-a-step waveform, which at minimum DC input comes out to a duty cycle of (0.8T/2)/T or 0.4. The magnitude of the current at the center of the ramp is the DC output current Idc, as can be seen from Figure 2.6 f.