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<< cont. from part 1 2.10.4 Primary rms Current, and Wire Size Calculation To simplify the primary current rms calculations, the ramponastep pulses will be approximated by "equivalent flattopped" pulses Iaft, whose amplitude is that at the center of the ramp or the DC output current Idc with a duty cycle of 0.4. Thus rms current in each half secondary is At 500 circular mils per rms ampere, the required number of circular mils for each half secondary is 2.11 Transistor Voltage Stress and Leakage Inductance Spikes It can be seen from the polarities of the transformer primary windings in FIG. 1 that when either transistor is "on," the opposite transistor's collector is subject to at least twice the DC supply voltage, since both half primaries have an equal number of turns and are in series, with the center tap connected to the supply. However, the maximum stress is somewhat more than twice the input voltage. An additional contribution comes from the socalled leakage inductance spikes shown in Figures 1a and 1c. These come about because there is effectively a small inductance (leakage inductance Ll ) in series with each half primary as shown in FIG. 7a. At the instant of turn "off," current in the transistor falls rapidly at a rate dI/dT, causing a positivegoing spike of amplitude e = Ll dI/dT at the bottom end of the leakage inductance. Conservative de sign practice assumes the leakage inductance spike may increase the stress voltage by as much as 30%, more than twice the maximum DC input voltage. Hence the transistors should be chosen so that they can tolerate with some safety margin a maximum voltage stress Vp of Vp = 1.3(2Vdc) (eqn. 15) The magnitude of the leakage inductance is not easily calculable. It can be minimized by use of a transformer core with a long center leg and by sandwiching the secondary windings (especially the higher current ones) in between halves of the primary. A good transformer should have leakage inductance of no more than 4%of its magnetizing inductance. TIP: The leakage inductance of any winding can be easily measured by short circuiting all other windings and measuring the residual inductance on the required winding. . Leakage inductance spikes can be minimized by addition of a snubber circuit (a capacitor, resistor, and diode combination) connected to the transistor collector as shown in FIG. 7a. Such configurations also serve the important function of reducing AC switching losses by load line shaping (phase shifting the overlap of falling transistor current and rising voltage at the collector). Detailed design of snubbers and some associated penalties they incur are discussed in Section 11.
Leakage inductance arises from the fact that some of the primary's magnetic flux lines do not return through the core and couple with the secondary windings. Instead, they return around the primary winding through a local air path as seen in FIG. 7b. The equivalent circuit of a core with its magnetizing Lm (see Section 2.6) and primary L1p leakage inductances is shown in FIG. 7c. Secondary leakage inductance arises from the fact that some of the secondary current's magnetic flux lines also do not couple with the primary but instead link the secondary windings via a local air path. But in most cases, there are fewer turns on the secondary than on the primary, and L1s can be neglected. The transformer equivalent circuit shown in FIG. 7c is a valuable tool in the understanding of many unexpected circuit effects and can be used up to about 300 to 500 kHz, where shunt parasitic capacitors across and between windings must also be taken into account.
2.12 Power Transistor Losses 2.12.1 AC Switching or CurrentVoltage "Overlap" Losses Leakage inductance in the power transformer allows a very rapid collector voltage fall time because for a short time when a transistor turns on, the leakage inductance has a very high impedance. Since the current cannot change instantaneously through an inductor, the collector current rises slowly during the turn "on" edge. Thus there is very little overlap of falling voltage and rising current at turn "on" and negligible switching loss. At turn "off," however, the inductance tends to maintain the previous current constant. Hence there is significant overlap and a worst case scenario may be assumed, such as that shown for the buck regulator of Figure 1.5b. The exact situation is shown in FIG. 8, where it is assumed that the current hangs on at its equivalent flat topped peak value Ipft (see Section 2.10.1) for the time it takes the voltage to rise from near zero to its maximum value of 2Vdc. The volt age then remains at 2Vdc during the time, Tcf, it takes the current to fall from Ipft to zero. Assuming Tvr = Tcf = Ts and a switching period T, the total switching dissipation per transistor per period Pt(ac) is Notice there are negligible switching losses at turn "on" because transformer leakage inductance causes a very fast voltage fall and a slow current rise. This results in very little turn "on" loss. However, worstcase scenario is shown at turn "off." The current remains constant at its peak Ipft until voltages rises to 2Vdc. The voltage remains at 2Vdc for the duration of the current fall time Tcf, producing a large turn "off" loss. 2.12.2 Transistor Conduction Losses The conduction losses are simply the transistor "on" voltage multi plied by the "on" current for each device averaged over a cycle, or It will be seen in Section 8 that a technique called Baker clamping can be used to reduce transistor storage times for bipolar base drives. This forces the collector "on" potential Vce to be about 1Vover a large range of current. Then for Ipft from Eqn. 9 we obtain 2.12.3 Typical Losses: 150W, 50kHz PushPull Converter It will be instructive to calculate the dissipation per transistor in a 150W pushpull converter at 50 kHz operating from a 48volt power source. The standard telephone industry power sources provide a nominal voltage of 48 V, with a minimum (Vdc) of 38 V and maximum (Vdc)of 60 V. It will be assumed that at 50 kHz, bipolar transistors will be used, and a reasonable value of the switching time (Ts as defined earlier) of 0.3 µs. The DC conduction losses from Eqn. 17 are Thus the AC overlap or switching losses are about 4.5 times greater than the DC conduction losses. If MOSFET transistors are considered with switching times Ts of about 0.05 µs, it can be seen that switching losses would be negligible in this example. 2.13 Output Power and Input Voltage Limitations in the PushPull Topology Aside from the fluximbalance problem in the pushpull topology, which does not exist in the currentmode controlled version, limitations include the useful power working area as defined in Eqn. 9, and input voltage in Eqn. 15. Equation 9 gives the peak current required of the transistor for a desired output power, and Eqn. 15 gives the maximum voltage stress on the transistor in terms of the maximum DC input voltage. These requirements limit the power rating of the pushpull topology to around 500 W when using bipolar transistors. Above that, it is difficult to find transistors that can meet the peak current and voltage stress while being fast enough with adequate gain. The technology is constantly improving, and without doubt a faster MOSFET with adequately high voltage and current ratings and sufficiently low "on" voltages would extend this power range. As an example, we will consider a 400W pushpull converter operating from telephone industry prime voltage source that is 48 V (nominal), 38 V (minimum), and 60 V (maximum). Equation 9 gives the peak current requirement as Ipft = 1.56Po /Vdc = 1.56(400)/38 = 16.4 A, and Eqn. 15 gives the maxi mum "off" voltage stress as Vp = 2.6Vdc = 2.6 × 60 = 156 V. To provide a margin of safety, a transistor with at least a 200V rating would be selected. A possible candidate would be the MJ13330 bipolar transistor. It has a 20A peak current rating, a Vceo rating of 200 V, and Vcer rating of 400 V (the voltage it can sustain when it has a negative bias of 1 to 5 V at turn "off"). It can thus meet the peak voltage and current stresses. At 16 amps, it has a maximum "on" saturation voltage of about 3 V, a minimum gain of about 5, and a storage time of 1.3 to 4 µs. However, with these limitations, it would have high DC and AC switching losses, have difficulty with flux imbalance (unless the currentmode version of pushpull were used), and would have difficulty operating above 40 kHz because of the long storage times. A potential MOSFET for such an application is the MTH30N20. This is a 30A, 200V device that at 16 A would have only 1.3 V "on" state voltage drop and hence half the DC conduction losses of the preceding bipolar transistor. With its fast switching times it would have quite low switching losses, but this and similar devices can be quite expensive. For offline converters, the pushpull topology is not very attractive due to the large voltage stress of 2.6 Vdc (see Eqn. 15). For example, with a 120VAC line input and±10%tolerance, the peak rectified DC voltage is 1.41×1.1×120 = 186 V. Hence during turn "off" at the top of the leakage spike, Eqn. 15 gives a peak stress of 2.6 × 186 = 484 V. We must also allow for transients in the supply above the maximum steadystate values. Transients are seldom specified for commercial power supplies, but conservative design practice assumes stress at least 15%above the maximum steadystate value, increasing the maximum stress to 1.15 × 484 or 557 V. Input voltage transients in special cases can be even greater, for example, the specifications on military aircraft given by Military Standard 704. Here the nominal voltage is 113 V AC but with a 10ms transient to 180 V AC, the peak "off" stress from Eqn. 42 would be 180 × 1.41 × 2.6 or 660 V. Although there are many fast bipolar transistors that can safely sustain voltages as high as 850 V with reverse input bias, clearly it is not good practice to use a topology that subjects the transistors to high voltage transients. Some topologies subject the transistors to only the normal maximum DC input voltage stress with no leakage spike. These are a better choice for high voltage and "offline" applications, not only because of the lesser voltage stress, but also because the smaller voltage excursion at turn "off" produces less EMI (electromagnetic interference). 2.14 Output Filter Design Relations 2.14.1 Output Inductor Design It was pointed out in Section 2.4 that in both master and slave out puts, the output inductors should not be permitted to go discontinuous. Remember, the discontinuousmode situation commences at the critical current where the inductor current ramp of Figure 6b has dropped to zero. This occurs when the DC current has dropped to half the ramp amplitude dI (see Section 3.6). Then FIG. 9 shows the output rectifier circuit for calculation of Lo ,Co . When Vdc is at its minimum, Ns will be chosen so that as V1 is at its minimum, Ton will not have to be greater than 0.8T/2 to yield the specified value of V . [...] where Lo is in henries Vo is in volts T is in seconds Idc is minimum output current in amperes Ion is nominal output current in amperes. 2.14.2 Output Capacitor Design The output capacitor Co is selected to meet the maximum output ripple voltage specification. In Section 3.7 it was shown that the output ripple is determined almost completely by the magnitude of the ESR (equivalent series resistance, Ro ) in the filter capacitor and not by the magnitude of the capacitor itself. The peaktopeak ripple voltage Vr is very closely equal to Vr = Ro dI ( eqn 21) where dI is the selected peaktopeak inductor ramp amplitude. However, it was pointed out that (for aluminum electrolytic capacitors) the product RoCo has been observed to be relatively constant over a large range of capacitor magnitudes and voltage ratings. For aluminum electrolytics, the product RoCo ranges between 50 and 80 × 10^6. Then Co is selected as: where Co is in farads for dI in amperes (see Eqn. 19) and Vr is in volts. 3. Forward Converter Topology 3.1 Basic Operation A typical triple output forward converter topology is shown in Figure 2.10. This topology is often chosen for output powers under 200 W with DC supply voltages in the range of 60 to 200 V. Below 60 V, the primary input current becomes uncomfortably large at the higher power levels. Above about 250 V, the maximum voltage stress on the transistors becomes uncomfortably large. Further, it will be shown that above output powers of 200Wor so, the primary input current becomes too large even at the higher supply voltages. We will see this from the following mathematical analysis. The topology is similar to the pushpull circuit of FIG. 1, but does not suffer from the latter's major shortcoming of flux imbalance, since it has one rather than two transistors. Compared with the push pull, at lower power it is more economical in cost and size. In FIG. 10 we see a master output Vom and two slaves, Vs1 and Vs2. A negativefeedback loop is closed around the master, and controls the Q1 "on" time so as to keep Vom constant against line and load changes. With an "on" time fixed by the master feedback loop, the slave outputs Vs1 and Vs2 are fully regulated against input volt age changes but only partly (about 5 to 8%) against load changes in themselves or in the master. The circuit works as follows. If we compare the forward converter with the pushpull of FIG. 1, we see that one of the transistors has been replaced by the diode D1.When Q1 is turned "on," the start of the primary winding Np (the dot end) and the start of all secondaries go positive. Current flows into the dot end of Np. At the same time, all rectifier diodes D2 to D4 are forwardbiased, and current flows out of the starts of all secondaries into the LC filters and the loads. Note that power flows into the loads when the power transistor Q1 is turned "on," hence the term forward converter. Both the pushpull and buck regulators deliver power to the loads when the power transistors are "on," so both are forward converters. FIG. 10 Forward converter topology and waveforms. In this example the feedback loop is closed around the chosen master output Vom, which is regulated against line and load changes. The two semiregulated slaves (Vs1 and Vs2) will be regulated against line changes only. In contrast, the boost regulator, the polarity inverter (see Figures 10 and 14), and the flyback type (which will be discussed in a later section) store energy in an inductor or transformer primary when the power transistor is "on" and deliver it to the load when the transistor turns "off." Such energy storage topologies can operate in either the discontinuous or continuous mode. These topologies are fundamentally different from the forward converters and were discussed in Sections 4.2 and 4.3. They will be taken up again in Section 4, which covers the flyback topology. Consider FIG. 10: if transistor Q1 has an "on" time of Ton, the voltage at the master rectifier cathode D5 is at a high level for a period of Ton. Assuming a 1V "on" voltage for Q1 and a rectifier forward drop of VD2, the highlevel voltage Vomr is The circuitry after the rectifier diode cathodes is exactly like that of the buck regulator of Figure 1.4. Diodes D5to D7 act like the free wheeling diode D1 of that figure. When Q1 turns "off," the current established in the magnetizing inductance of T1 while Q1 was "on" (recall the equivalent circuit of a transformer as in FIG. 7c) reverses the polarity of the voltage across Np. Now all the starts (dot ends) of primary and secondary windings go negative. Without the "catch" action of diode D1, the dot end of Nr would go very far negative; since Np and Nr usually have equal turns, the nodot end of Np would go sufficiently positive to avalanche Q1 and destroy it. However, with the catch action of diode D1, the dot end of Nr will be clamped at one diode drop below ground. If there were no leakage inductance in T1 (recall again the equivalent circuit of a transformer as in Figure 7c), the voltage across Np would equal that across Nr . Assuming that the 1V forward drop across D1 can be neglected, the voltage across Nr and Np is Vdc, and the voltage at the nodot end of Np and at the Q1 collector is then 2 Vdc. We have seen previously that within one cycle, if a core has moved in one direction on its hysteresis loop, it must be restored to exactly its original position on the loop before it can be allowed to move in the same direction again in the next cycle. Otherwise, after many cycles, the core will "staircase" into saturation. If this is allowed to happen, the core will not be able to support the applied voltage, and the transistor will be destroyed. FIG. 10 shows that when Q1 is "on" for a time Ton, Np is subjected to voltsecond product VdcTon with its dotend positive, that voltsecond product is the area A1 in FIG. 10. By Faraday's law (see Eqn. 17), that voltsecond product causessay, a positiveflux change dB =(VdcTon/Np Ae ) 10^8 gauss. When Q1 turns "off," and the magnetizing inductance has reversed the polarity across Np and kept its nodot end at 2Vdc long enough for the voltsecond area product A2 in FIG. 10 to equal area A1, the core has been restored to its original position on the hysteresis loop, and the next cycle can safely start. We can see that the "reset volt seconds" has equaled the "set voltseconds." When Q1 turns "off," the dot ends of all secondaries go negative with respect to their nodot ends. Current in all output inductors L1 to L3 will try to decrease. Since current in inductors cannot change instantaneously, the polarity across all inductors reverses in an attempt to maintain the current's constant. The input ends of the inductors try to go far negative, but are caught at one diode drop below out put ground by freewheeling diodes D5 to D7 (see FIG. 10), and rectifier diodes D2 to D4 are reversebiased. Inductor current now continues to flow in the same direction through the output end, returning through the load, partly through the filter capacitor, up through the freewheeling diode and back into the inductor. Voltage at the cathode of the main diode rectifier D2 is then as shown in FIG. 11b. It is high at a level of [(Vdc 1)(Nm/Np)]VD2 for time Ton, and for a time T  Ton it is one freewheeling diode (D5) drop below ground. The LC filter averages this waveform, and assuming that the forward drop across D5 equals that across D2(= Vd ), the DC output voltage at V is 3.2 Design Relations: Output/Input Voltage, "On" Time, Turns Ratios The negativefeedback loop senses a fraction of Vom, compares it with the reference voltage Vref, and varies Ton so as to keep Vom constant for any changes in Vdc or load current. From Eqn. 24 it can be seen that as Vdc changes, the feedback loop keeps the output constant by keeping the product VdcTon constant. Thus maximum Ton(Ton) will occur at minimum specified Vdc(Vdc), and Eqn. 24 can be rewritten for minimum DC input voltage as In relation in Eqn. 25, a number of design decisions must be made in the proper sequence. First, the minimum DC input voltage Vdc is specified. Then the maximum permitted "on" time Ton, which occurs at Vdc (minimum Vdc), will be set at 80% of a half period.
This margin is included to ensure (see FIG. 10) that the area A2 can equal A1. If the "on" time were permitted to go to a full half period, A2 would just barely equal A1 at the start of the next full cycle. Then any small increase in "on" time due to storage time changes with temperature or production spreads would not permit A2 to equal A1. The core would not be completely reset to its starting point on the hysteresis loop; it would drift up into saturation after a few cycles and destroy the transistor. Next the number of primary turns Np is established from Faraday's law (see Eqn. 17) for Vdc, and a certain specified flux change dB in the time Ton. Limits on that flux change are similar to those described for the pushpull topology in Section 1.5.9 and will also be discussed later. Thus, in Eqn. 25, Vdc, Ton,T, and Vd are specified, and Np is calculated from Faraday's law. This fixes the number of main secondary turns Nm needed to achieve the required main output voltage Vom. 3.3 Slave Output Voltages The slave output filters L2, C2 and L3, C3 average the width modulated rectangular waveforms at their respective rectifier cathodes. The waveform upper levels are [(Vdc  1)(Ns1/Np)]  Vd3 and [(Vdc 1)(Ns2/Np)]Vd4, respectively. The low level voltages are one diode drop belowground. They are at the high level for the same maximum Ton as is the main secondary, when the input DC input voltage is at the specified minimum Vdc. Again assuming that the forward rectifier and freewheeling diode drops equal Vd , the slave output voltages at low line Vdc are By regulating Vom, the feedback loop keeps VdcTon constant, but that same product appears in Eqs. 26 and 27, and hence the slave out puts remain constant as Vdc varies. It can be seen from Eqn. 24 and FIG. 14 that the negative feedback loop keeps the main output constant for either line or load changes by appropriately controlling Ton period, so that the sampled output is equal to the reference voltage Vref. This is not so obvious for load changes, since load current does not appear directly in Eq. 24, but it does appear indirectly. Load changes will change the "on" voltage of Q1 (assumed as 1 V heretofore) and the forward drop in the rectifier diode. Although these changes are small, they will cause small changes in the output voltage that will be sensed and corrected by the error amplifier by making a small change in Ton. Moreover, as can be seen in Eqs. 26 and 27, any change in Ton without a corresponding change in Vdc will cause the slave output volt ages to change. The slave output voltages also change with changes in their own load currents. As those currents change, the rectifier forward drops also change, causing a change in the peak voltage at the input to the LC averaging filter. So slave output voltages will change the peak voltages to the averaging filters, with no corresponding change in Ton. Such changes in the slave output voltages as a result of load changes in the master and slave can be limited to within 5 to 8%. As discussed in Section 2.4, neither master nor slave output inductors can be permitted to go discontinuous at their minimum load currents. This is ensured by choosing appropriately large output inductors, as will be described next. The number of slave secondary turns Ns1, Ns2 are calculated from Eqs. 26 and 27, as all parameters there are either specified, or calculated from specified values. The parameters Vdc, T, and Vd are all specified, and Ton is set at 0.8T/2 as discussed earlier; Np is calculated from Faraday's law (see Eqn. 17) as described earlier. 3.4 Secondary Load, FreeWheeling Diode, and Inductor Currents Knowledge about the amplitudes and wave shapes of the various out put currents is needed to select secondary and output inductor wire sizes and current ratings of the rectifiers and freewheeling diodes. As described for the buck regulator in Section 3.2, secondary cur rent during the Q1 "on" time has the shape of an upwardsloping ramp sitting on a step (see FIG. 11c) because of the constant volt age across the inductor during this time, with its input end positive with respect to the output end. When Q1 turns "off," the input end of the inductor is negative with respect to the output end and inductor current ramps downward. The freewheeling diode, at the instant of turn "off," picks up exactly the inductor current that had been flowing just prior to turn "off." That diode current then ramps downward (FIG. 11d), as it is in series with the inductor. Inductor current is the sum of the secondary current when Q1 is "on" plus the freewheeling diode current when Q1 is "off," and is shown in FIG. 11e. Current at the center of the ramp in any of FIG. 11c, 11d, or 11e is equal to the DC output current. 3.5 Relations Between Primary Current, Output Power, and Input Voltage Assume an efficiency of 80% of the total output power from all secondaries to the DC power at the input voltage node. Then Po = 0.8Pin or Pin = 1.25Po . Now calculate Pin at minimum DC input voltage Vdc, which is Vdc times the average primary current at minimum DC input. All secondary currents have the waveshape of a ramp sitting on a step because all secondaries have output inductors. These ramp onastep waveforms have a width of 0.8T/2 at minimum DC input voltage. All these secondary currents are reflected into the primary by their turns ratios, and hence the primary current pulse is a single ramponastep waveform of width 0.8T/2. There is only one such pulse per period (see FIG. 10) as this is a singletransistor circuit. The duty cycle of this primary pulse is then (0.8T/2)/T or 0.4. Like the pushpull topology, this ramponastep can be approximated by an equivalent flattopped pulse Ipft of the same width and whose amplitude is that at the center of the ramp. The average value of this current is then 0.4Ipft. Then This is a valuable relation. It gives the equivalent peak flattopped primary current pulse amplitude in terms of what is known at the outsetthe minimum DC input voltage and the total output power. This permits an immediate selection of a transistor with adequate current rating and gain if it is a bipolar transistor, or with sufficiently low "on" resistance if it is a MOSFET type. For a forward converter, Eqn. 28 shows Ipft has twice the amplitude of that required in a pushpull topology (see Eqn. 9) at the same output power and minimum DC input voltage. This is obvious, because the pushpull has two pulses of current or power per period as compared with a single pulse in the forward converter. From Eqn. 25, if the number of secondary turns in the for ward converter is chosen large enough, then the maximum "on" time at minimum DC input voltage will not need to be greater than 80% of a half period. Then, as seen in FIG. 10, the area A2 can always equal A1 before the start of the next period. The core is then always reset to the same point on its hysteresis loop within one cycle and can never walk up into saturation. The penalty paid for this guarantee that flux walking cannot occur in the forward converter is that the primary peak current is twice that for a pushpull at the same output power. Despite all the precautions described in Section 2.8, however, there is never complete certainty in the pushpull that flux imbalance will not occur under unusual dynamic load or line conditions. 3.6 Maximum OffVoltage Stress in Power Transistor In the forward converter, with the number of turns on the reset winding Nr equal to that on the power winding Np, maximum offvoltage stress on the power transistor is twice the maximum DC input volt age plus a leakage inductance spike. These spikes and their origin and minimization have been discussed in Section 2.11. Conservative design, even with all precautions to minimize leakage spikes, should assume they may be 30% above twice the maximum DC input volt age. Maximum offvoltage stress is then the same as in the pushpull and is Vms = 1.3(2Vdc) (eqn 29) 3.7 Practical Input Voltage/ Output Power Limits It was stated at the outset in Section 3.1 that the practical maximum output power limit for a forward converter whose maximum DC input voltage is under 60 V is 150 to 200 W. This is so because the peak primary current as calculated from Eqn. 28 becomes excessive, as there is only a single pulse per period as compared with two in the pushpull topology. Thus consider a 200Wforwardconverter for the telephone industry in which the specified minimum and maximum input voltages are 38 and 60 V, respectively. Peak primary current from Eqn. 28 is Ipft = 3.13Po /Vdc = 3.13(200)/38 = 16.5 A, and from Eqn. 29, maximum offvoltage stress is Vms = 2.6Vdc = 2.6 × 60 = 156 V. To provide a safety margin, a device with at least a 200V rating would be used to provide protection against input voltage transients that could drive the DC input above the maximum steadystate value of 60 V. Transistors with 200V, 16A ratings are available, but they all have drawbacks as discussed in Section 2.13. Bipolar transistors are slow, and MOSFETs are easily fast enough but expensive. For such a 200W application, a pushpull version guaranteed to be free from flux imbalance would be preferable; with two pulses of current per period, peak current would be only 8 A. With the resulting lower peak current noise spikes on the ground buses, the radiofrequency interference (RFI) would be considerably lowera very important consideration for a telephone industry power supply. Such a flux imbalancefree topology is current mode, which is discussed later. The forward converter topology, like the pushpull (discussed in Section 2.13), has the same difficulty in coping with maximum volt age stress in an offline converter where the nominal AC input voltage is 120 ± 10%. At high line, the rectified DC input is 1.1 × 120 × 1.41 = 186 V minus 2 V for the rectifier diode drops or 184 V. From Eq. 29, the maximum voltage stress on the transistor in the "off" state is Vms = 2.6 × 184 = 478 V. At minimum AC input voltage, the rectified DC output is Vdc = (0.9 × 120 × 1.41)  2 = 150 V, and from Eqn. 28, the peak primary current is Ipft = 3.13 × 22/150 = 4.17 A. Thus, for a 200W offline forward converter the problem is more the 478V maximum voltage stress than the 4.17A peak primary cur rent stress. As was seen in Section 2.13, when a 15% input transient is taken into account, the peak offvoltage stress is 550 V. With a bipolar transistor operating under Vcev conditions (reverse input bias of 1to 5 V at the instant of turn "off"), a voltage stress of even 550 V is not a serious restriction. Many devices have 650 to 850V Vcev ratings and high gain, low "on" drop, and high speed at 4.17 A. But, as discussed in Section 2.13, there are preferable topologies, discussed next, that subject the off transistor to only Vdc and not twice Vdc. 3.8 Forward Converter With Unequal Power and Reset Winding Turns Heretofore it has been assumed that the numbers of turns on the power winding Np and the reset winding Nr are equal. Some advantages result if Nr is made less or greater than Np. The number of primary power turns Np is always chosen by Faraday's law and will be discussed in Section 3.10.2. If Nr is chosen less than Np, the peak current required for a given output power is less than that calculated from Eqn. 28, but the maximum Q1 offvoltage stress is greater than that calculated from Eqn. 29. If Nr is chosen larger than Np, the maximum Q1 offvoltage stress is less than that calculated from Eqn. 29, but the peak primary current for a given output power is greater than that calculated from Eqn. 28. This can be seen from FIG. 12 as follows. When Q1 turns "off," polarities across Np and Nr reverse; the dot end of Nr goes negative and is caught at ground by catch diode D1. Transformer T1 is now an autotransformer. There is a voltage Vdc across Nr and hence a voltage Np/Nr (Vdc) across Np. The core is set by the voltsecond product by VdcTon during the "on" time and must be reset to its original place on the hysteresis loop by an equal voltsecond product. That reset voltsecond product is Np/Nr (Vdc)Tr . FIG. 12 Forward convertercollectortoemitter voltages for three Np to Nr ratios. Note in all cases that reset voltsecond product equals set voltsecond product. (a) Switching frequency, (b)Np = Nr ,(c)Np > Nr , (d)Np < Nr . When Nr equals Np, the reset voltage equals the set voltage, and the reset time is equal to the set time (area A1 = area A2) as seen in Figure 12b. For Nr = Np, the maximum Q1 "on" time that occurs at minimum DC input voltage is chosen as 0.8T/2 to ensure that the core is reset before the start of the next period; Ton + Tr is then 0.8T. Now if Nr is less than Np, the resetting voltage is larger than Vdc and consequently Tr can be smaller (area A3 = area A4) as shown in Figure 12c.With a shorter Tr ,Ton can be longer than 0.8T/2, and Ton+Tr can still be 0.8T so that the core is reset before the start of the next period. With a longer Ton, the peak current is smaller for the same average current and the same average output power. Thus in FIG. 12c, a smaller peak current stress has been traded for a longer voltage stress than in FIG. 12b. With Nr greater than Np, the reset voltage is less than Vdc. Then if Ton + Tr is still to equal 0.8T, and the reset voltseconds is to equal the set voltseconds (area A5 = area A6 in FIG. 12d), Tr must be longer and Ton must be shorter than 0.8T/2, as the reset voltage is less than the set voltage. With Ton less than 0.8T/2, the peak current must be higher for the same average current. Thus, in FIG. 12d, a lesser voltage stress has been achieved at the cost of a higher peak current for the same output power as in FIG. 12b. This can be seen quantitatively as [...] 3.9 Forward Converter Magnetics 3.9.1 FirstQuadrant Operation Only The transformer core in the forward converter operates in the first quadrant of the hysteresis loop only. This can be seen in FIG. 10. When Q1 is "on," the dot end of T1 is positive with respect to the nodot end, and the core is driven, say, in a positive direction on the hysteresis loop, and the magnetizing current ramps up linearly in the magnetizing inductance. When Q1 turns "off," stored current in the magnetizing inductance reverses the polarity of voltages on all windings. The dot end of Nr goes negative until it is caught one diode drop belowground by catch diode D1. Now the magnetizing current that is stored in the magnetic core continues to flow. It simply transfers from Np, where it had ramped upward during the Q1 "on" time, into Nr where it ramps back to zero during the "off" time. It flows out of the nodot end of Nr into the positive end of the supply voltage Vdc, out of the negative end of Vdc, through D1, and back into Nr . Since the dot end of Nr is positive with respect to its nodot end during the Q1 "off" time, the magnetizing current Id ramps linearly downward, as can be seen in FIG. 10. When it has ramped down to zero (at the end of area A2 in FIG. 10), there is no longer any stored energy in the magnetizing inductance and nothing to hold the dot end of Nr below the D1 cathode. The voltage at the dot end of Nr starts rising toward that at the D1 cathode. The voltage at the dot end of Nr starts rising toward Vdc, and that at the nodot end of Np (Q1 collector) starts falling from 2Vdc back down toward Vdc. Thus operation on the hysteresis loop is centered about half the peak magnetizing current (VdcTon/2Lm). Nothing ever reverses the direction of the magnetizing currentit simply builds up linearly to a peak and relaxes back down linearly to zero. This firstquadrant operation has some favorable and some un favorable consequences. First, compared with a pushpull circuit, it halves the available output power from a given core. This can be seen from Faraday's law (see Eqn. 17), which fixes the number of turns on the primary. By solving Faraday's law for the number of primary turns, we get Np = Edt/Ae dB × 10^8. If dB in the forward converter is limited to an excursion from zero to some Bmax, instead of from Bmax to +Bmax as in a pushpull topology, the number of primary turns for the for ward converter will be twice that in each half primary of a pushpull operating from the same Vdc. Although the pushpull has two half primaries, each of which must support the same voltsecond product as the forward converter primary, the pushpull provides two power pulses per period as compared with one for the forward converter. The end result is that a core used in a forward converter can process only half the output power available from the same core in a pushpull configuration. However, the pushpull core at twice the output power will run somewhat warmer, as its flux excursion is twice that of the forward converter. Since core losses are proportional to the area of the hysteresis loop traversed, the pushpull core losses are twice that of the forward converter. Yet total copper losses in both half primaries of a pushpull are no greater than that of a forward converter of half the output power, because the rms current in each pushpull half primary is equal to that in the forward converter primary. Since the number of turns in each pushpull half primary is half that of the forward converter primary of half the output power, they also have half the resistance. Thus total copper loss in a forward converter is equal to the total loss of the two half primaries in a pushpull of twice the output power. 3.9.2 Core Gapping in a Forward Converter In FIG. 3, we see the hysteresis loop of a ferrite core with no air gap. We see that at zero magnetizing force (0 Oe) there is a residual magnetic flux density of about ± 1000 G. This residual flux is referred to as remanence. In a forward converter, if the core started at 0 Oe and hence at 1000 G, the maximum flux change in dB possible before the core is driven up into the curved part of the hysteresis loop is about 1000 G. It is desirable to stay off the curved part of the hysteresis loop, and hence the forward converter core with no air gap is restricted to a maximum dB of 1000G.As shown earlier, the number of primary turns is inversely proportional to dB. Such a relatively small dB requires a relatively large number of primary turns. A large number of primary turns requires small wire size and hence decreases the current and power available from the transformer. By introducing an air gap in the core, the hysteresis loop is tilted as shown in FIG. 5, and magnetic remanence is reduced significantly. The hysteresis loop tilts over but still crosses the H (coercive force) axis with zero flux density at the same point. Coercive force for ferrites is seen to be about 0.2 Oe in FIG. 3. An air gap of 2 to 4 mils will reduce remanence to about 200 G for most cores used at 200 to 500W of output power. With remanence of 200 G, the dB before the core enters the curved part of the hysteresis loop is now about 1800 G, and fewer turns are permissible. However, a penalty is paid in introducing an air gap. FIG. 5 shows the slope of the hysteresis loop tilted over. The slope is dB/dH or core permeability, which has been decreased by adding the gap. Decreasing permeability decreases magnetizing inductance and in creases magnetizing current (Im = VdcTon/Lm). Magnetizing current contributes no output power to the load; it simply moves the operating point of the core around the hysteresis loop and contributes significant copper loss if it exceeds 10% of the primary load current. 3.9.3 Magnetizing Inductance with Gapped Core Magnetizing inductance with a gapped core can be calculated as follows. Voltage across the magnetizing inductance is LmdIm/dt and from Faraday's law: [...] A useful way of looking at a gapped core is to examine the denominator in Eqn. 38. In most cases, u is so high that the term li /u is small compared with the air gap la , and the inductance is determined primarily by the length of the air gap. 3.10 Power Transformer Design Relations 3.10.1 Core Selection As discussed in Section 2.9.1 on core selection for a pushpull trans former, the amount of power available from a core for a forward converter transformer is related to the same parameterspeak flux density, core iron and window areas, frequency, and coil current density in circular mils per rms ampere. In Section 7, an equation will be derived giving the amount of available output power as a function of these parameters. This equation will be converted to a chart that permits selection of core size and operating frequency at a glance. For the present, it is assumed that a core has been selected and that its iron and window areas are known. 3.10.2 Primary Turns Calculation The number of primary turns is calculated from Faraday's law as given in Eqn. 7. From Section 3.9.2, we see that in the forward converter with a gapped core, flux density moves from about 200 G to some higher value Bmax. In the pushpull topology as discussed in Section 2.9.4, this peak value will be set at 1600 G (for ferrites at low frequencies, where core losses are not a limiting factor). This avoids the problem of a much larger and more dangerous flux swing due to rapid changes in DC input voltage or load currents. Such rapid changes are not immediately compensated because the limited erroramplifier bandwidth can't correct the power transistor "on" time fast enough. During this erroramplifier delay, the peak flux density can exceed the calculated normal steadystate value for a number of cycles. This can be tolerated if the normal peak flux density in the absence of a line or load transient is set to the low value of 1600 G. As discussed earlier, the excursion from approximately zero to 1600 G will take place in 80%of a half period to ensure that the core can be reset before the start of the next period (see FIG. 12b). Thus, the number of primary turns is set by Faraday's law at where Vdc = minimum DC input, V T = operating period, s Ae = iron area, cm^2 dB = change in flux density, G 3.10.3 Secondary Turns Calculation Secondary turns are calculated from Eqs. 25 to 27. In those relations, all values except the secondary turns are specified or already calculated. Thus (see FIG. 10): Vdc = minimum DC input, V Ton = maximum "on" time, s(= 0.8T/2) Nm, Ns1, Ns2 = numbers of main and slave turns Np = number of primary turns Vd = rectifier forward drop If the main output produces 5 V at high current as is often the case, a Schottky diode with forward drop of about 0.5 V is typically used. The slaves usually have higher output voltages that require the use of fastrecovery diodes with higher reversevoltage ratings. Such diodes have forward drops of about 1.0 V over a large range of current. 3.10.4 Primary rms Current and Wire Size Selection Primary equivalent flattopped current is given by Eqn. 28. That cur rent flows for a maximum of 80%of a half period per period, so its maximum duty cycle is 0.4. Recalling that the rms value of a flattopped If the wire size is chosen on the basis of 500 circular mils per rms ampere, the required number of circular mils is 3.10.5 Secondary rms Current and Wire Size Selection It is seen in FIG. 11 that the secondary current has the characteristic shape of a ramp on a step. The pulse amplitude at the center of the ramp is equal to the average DC output current. Thus, the equivalent flattopped secondary current pulse at Vdc (when its width is a maxi mum) has amplitude Idc, width 0.8T/2, and duty cycle (0.8T/2)/T or 0.4. Then ...and at 500 circular mils per rms ampere, the required number of circular mils for each secondary is ... 3.10.6 Reset Winding rms Current and Wire Size Selection The reset winding carries only magnetizing current, as can be seen by the dots in FIG. 10.When Q1 is "on," diode D1 is reversebiased, and no current flows in the reset winding. But magnetizing current builds up linearly in the power winding Np. When Q1 turns "off," that magnetizing current must continue to flow. When Q1 current ceases, the current in the magnetizing inductance reverses all winding voltage polarities. When D1 clamps the dot end of Nr to ground, the magnetizing current transfers from Np to Nr and continues flowing through the DC input voltage source Vdc, through D1, and back into Nr . Since the nodot end of Nr is positive with respect to the dot end, the magnetizing current ramps downward to zero as seen in FIG. 10. The waveshape of this Nr current is the same as that of the magnetizing current that ramped upward when Q1 was "on," but it is reversed from left to right. Thus the peak of this triangle of current is Ip(magnetizing) = VdcTon/Lmg, where Lmg is the magnetizing inductance with an air gap as calculated from Eqn. 39. The inductance without the gap is calculated from the ferrite catalog value of Al , the inductance per 1000 turns. Since inductance is proportional to the square of the number of turns, inductance for n turns is Ln = Al (n/1000) 2. The duration of this current triangle is 0.8T/2 (the time required for the core to reset), and it comes at a duty cycle of 0.4. It is known that the rms value of a repeating triangle waveform (no spacing between successive triangles) of peak amplitude Ip is Irms = Ip v3. But this triangle comes at a duty cycle of 0.4, and hence its rms value is ... and at 500 circular mils per rms ampere, the required number of circular mils for the reset winding is ... Most frequently, the magnetizing current is so small that the reset winding wire can be No. 30 AWG or smaller. 3.11 Output Filter Design Relations The output filters L1C1, L2C2, and L3C3 average the voltage wave form at the rectifier cathodes. The inductor is selected to operate in continuous mode (see Section 3.6) at the minimum DC output cur rent. The capacitor is selected to yield a specified minimum output ripple voltage. 3.11.1 Output Inductor Design Recall from Section 3.6 that discontinuous mode condition occurs when the inductor current ramp drops to zero (see FIG. 10). Since the DC output current is the value at the center of the ramp, discontinuous mode occurs at a minimum current Idc equal to half the ramp amplitude dI as can be seen in FIG. 10. 3.11.2 Output Capacitor Design It was seen in Section 3.7 that the output ripple is almost completely determine d by the equivalent series resistance Ro of the filter capacitor. The peaktopeak ripple amplitude is Vor = Ro dI, where dI is the peak topeak ripple current amplitude chosen by the selection of the ripple inductor as discussed earlier. Assuming that the average value of RoCo for aluminum electrolytic capacitors over a large range of voltage and capacitance ratings is given by RoCo =65 × 10^6 as in Section 1.3.7, then ... ...where dI is in amperes and Vor is in volts for Co in farads.

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