Solid-State Electronic Devices: High-Frequency, High-Power and Nanoelectronic Devices [part 2]

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5. The Semiconductor-Controlled Rectifier

FIG. 13 A semiconductor controlled rectifier: (a) four-layer geometry and common circuit symbols; (b) I-V characteristics.

The semiconductor-controlled rectifier (SCR) is useful in many applications, such as power switching and various control circuits. This device can handle currents from a few milliamperes to hundreds of amperes. Since it can be turned on externally, the SCR can be used to regulate the amount of power delivered to a load simply by passing current only during selected portions of the line cycle. A common example of this application is the light-dimmer switch used in many homes. At a given setting of this switch, an SCR is turned on and off repetitively, such that all or only part of each power cycle is delivered to the lights. As a result, the light intensity can be varied continuously from full to dark. The same control principle can be applied to motors, heaters, and many other systems. We shall discuss this type of application next, after first establishing the fundamentals of device operation.

[ This device is often called a thyristor to indicate its function as a solid state analogue of the gas thyratron, a gas-filled tube that passes current when an arc discharge occurs at a critical firing voltage. In a manner analogous to the gate current control of the SCR, this firing voltage can be varied by a voltage applied to a third electrode.]

The most important four-layer device in power circuit applications is the three-terminal SCR6 (FIG. 13). This device is similar to the p-n-p-n diode, except that a third lead (gate) is attached to one of the base regions.

When the SCR is biased in the forward-blocking state, a small current supplied to the gate can initiate switching to the conducting state. As a result, the anode switching voltage VP decreases as the current iG applied to the gate is increased (FIG. 13b). This type of turn-on control makes the SCR a useful and versatile device in switching and control circuits (FIG. 14).

To visualize the gate-triggering mechanism, let us assume that the device is in the forward-blocking state, with a small saturation current flowing from anode to cathode. A positive gate current causes holes to flow from the gate into p2, the base of the n-p-n transistor. This added supply of holes and the accompanying injection of electrons from n2 into p2 initiates transistor action in the n-p-n. After a transit time vt2, the electrons injected by j3 arrive at the center junction and are swept into n1, the base of the p-n-p. This causes an increase in hole injection of j1, and these holes diffuse across the base n1 in a transit time vt1. Thus, after a delay time of approximately vt1 + vt2, transistor action is established across the entire p-n-p-n, and the device is driven into the forward-conducting state. In most SCRs, the delay time is less than a few microseconds and the gate current required for turn-on is only a few milliamperes. Therefore, the SCR can be turned on by a very small amount of power in the gate circuit. On the other hand, the device current i can be many amperes, and the power controlled by the device may be very large.

It is not necessary to maintain the gate current once the SCR switches to the conducting state; in fact, the gate essentially loses control of the device after regenerative transistor action is initiated. For most devices, a gate current pulse lasting a few microseconds is sufficient to ensure switching.

Ratings of minimum gate pulse height and duration are generally provided for particular SCR devices.

FIG. 14 Example of the use of an SCR to control the power delivered to a load: (a) schematic diagram of the circuit; (b) waveforms of the delivered signal and the phase-variable trigger pulse.

5.1 Turning Off the SCR

Turning off the SCR-changing it from the conducting state to the blocking state-can be accomplished by reducing the current i below a critical value (called the holding current) required to maintain the c1 + c2 = 1 condition.

In some SCR devices, gate turnoff can be used to reduce the alpha sum below unity. For example, if the gate voltage is reversed in FIG. 14, holes are extracted from the p2 base region. If the rate of hole extraction by the gate is sufficient to remove the n-p-n transistor from saturation, the device turns off.

However, there are often problems involving the lateral flow of current in p2 to the gate; nonuniform biasing of j3 can result from the fact that the bias on this emitter junction varies with position when a lateral current flows. Therefore, SCR devices must be specifically designed for turn-off control; at best, this turn-off capability can be utilized only over a limited range for a given device.

6. Insulated Gate Bipolar Transistor

We saw in Section 5 that the SCR has difficulty in efficiently turning off the device using the gate. We need to use additional circuitry to reduce the anode to-cathode current below the holding current to change the SCR from the conducting state to the blocking state. This is, of course, clumsy and expensive.

Hence, the insulated-gate bipolar transistor (IGBT) was invented by Baliga in 1979 to address this issue. This variation on the SCR can easily be turned off from the conducting to the blocking state by the action of the gate.

This device is also known by several other names, such as conductivity-modulated FET (COMFET), insulated-gate transistor (IGT), insulated-gate rectifier (IGR), gain-enhanced MOSFET (GEMFET), and bipolar FET (BiFET).

FIG. 15 Structure of an insulated-gate bipolar transistor.

The basic structure is shown for an n-channel device in FIG. 15. It combines an SCR with a MOSFET that is able to connect or disconnect the n+ cathode to the n-base region, depending on the gate bias of the MOSFET. The MOSFET channel length is determined by the p region, which is formed by diffusion of the acceptors implanted in the same region as the n+ cathode. In other words, the channel length is determined not by the lithography of the gate, as in a conventional MOSFET but rather by the diffusion of the acceptors. Such a MOSFET structure is known as a double-diffused MOSFET (DMOS). The DMOS device is essentially an NMOSFET.

The main part of the IGBT is the n-region, which acts as the drain of the DMOS device. This is generally a thick (~50 mm) epitaxial region with a low doping (~10^14 cm^-3 ) grown on a heavily p+ - doped substrate that forms the anode. The n- region can therefore support a large blocking voltage in the "off" state. In the "on" state, the conductivity of this lightly doped region is modulated (increased) by the electrons injected from the n+ cathode and the holes injected from the p+ anode-hence the alternative name conductivity-modulated FET (COMFET). The increased conductivity allows the voltage drop across the device to be minimal in the "on" state.

The I-V characteristics are shown in FIG. 16. If the DMOS gate voltage is zero (or below the threshold voltage), an n-type inversion region is not formed in the p-type channel region and the n+ cathode is not shorted to the n-base. The structure then looks exactly like a conventional SCR that allows minimum current flow in either polarity until breakdown is reached.

For positive anode-to-cathode bias V AK, avalanche breakdown occurs at the n- - p junction, while for negative V AK avalanche occurs at the n- - p+ junction.

FIG. 16 Output I-V characteristics of an insulated-gate bipolar transistor (n channel).

FIG. 17 IGBT equivalent circuit: (a) below the offset voltage, for low VAK; (b) above the offset voltage, for high VAK.

When a gate bias is applied to the DMOS gate, we see that, for positive V AK, there is significant current flow (FIG. 17). The characteristics look like that of a MOSFET, with one difference: Instead of the current starting to increase from the origin, there is an offset or cut-in voltage of ~0.7 V, as with a diode. The reason for this can be understood by looking at the equivalent circuit in FIG. 17a. For small V AK up to the offset voltage, the structure looks like a DMOS in series with a p-i-n diode made up of the p+ substrate (the anode), the n-blocking region (the base), which is essentially like an intrinsic region, and the n+ cathode. In this regime, there is negligible volt age drop across the DMOS device, and the p-i-n device is in forward bias.

The injected carriers from the anode and the cathode recombine in the n- region. As we saw in Section 5, for a diode dominated by recombination in the depletion region, the I-V characteristics show an exponential behavior, with a diode ideality factor of n = 2. Therefore, in this region, we get

IA ? exp(qV AK / 2kT) (eqn. 8)

On the other hand, when V AK is larger than the offset voltage (~0.7 V), the characteristics look like that of a MOSFET, multiplied by a p-n-p bipolar junction transistor gain term. The equivalent circuit in this region is shown in FIG. 17b. In this regime, not all the injected carriers recombine in the near-intrinsic n-region. The current they supply, which is essentially the DMOSFET current IMOS, acts as the base current of the vertical p-n-p BJT formed between the p+ substrate (anode), the n-base, and the p-channel of the DMOS device. Hence, the current is now given by

IA = (1 + bpnp)IMOS (eqn. 9)

The shape of the characteristics looks like that of the DMOS device.

This is the preferred mode of operation of the IGBT.

Finally, if the current levels are too high, the IGBT latches into a low impedance state like that of a conventional SCR in the "on" state. This is undesirable, because it means that the gate of the DMOS device has now lost control.

The IGBT clearly incorporates some of the best features of MOSFETs and BJTs. Like a MOSFET, it has high input impedance and low input capacitance. On the other hand, in the "on" state, it has low resistance and high current-handling capability, like a BJT or an SCR. Because of these factors, and because it can turn off more easily than an SCR, the IGBT is gradually becoming the power device of choice, in place of the more traditional SCR.

7. Nanoelectronic Devices

Nanotechnology is sometimes defined as engineered objects in the length scale of 1-100 nm with novel, useful properties. This nanoscale regime, some times also known as the mesoscale, lies between the microscale (~microns) and atomic/molecular scale (~0.1 nm). When objects are shrunk from the macro to microscale and beyond, they don't just become smaller, but they also behave differently. One way to appreciate this is if one considers the fraction of atoms that lie at the surface of a sphere. For macroscopic or microscopic dimensions, the vast majority of the atoms are found to lie in the bulk of the sphere. As one enters the mesoscale, a substantial fraction of the atoms are found to be at the surface, which very often have different properties than bulk atoms. In other words, at some point smaller isn't just smaller but "smaller is different." On the other hand, if one considers much smaller objects such as atoms/molecules, their properties belong to the realm of quantum mechanics and chemistry. Now, if one considers clusters of these atoms/molecules, as in a nanoscale object, because of collective effects between these atoms, new properties can emerge that are not manifested by the individual atoms. The physicist, Philip Anderson, eloquently described this as "more is different!"

There are many nanoelectonic devices that are being investigated in research labs. We will briefly discuss a few interesting examples which show novel, nanoscale properties, according to the dimensionality of the nano-device: zero-dimensional quantum dots, one-dimensional quantum wires and nanotubes, and two-dimensional layered crystals such as grapheme. Many of the novel properties arise from the density of states of these low dimensionality systems discussed in Appendix IV.

7.1 Zero-Dimensional Quantum Dots

Zero-dimensional quantum dot systems have singularities in the density of states, where N(E) varies as 1/E. These are sometimes called "artificial atoms." However, the analogy is not perfect. While atoms have a spherically symmetric Coulomb potential, V(r) ~ 1/r, leading to energy levels that vary as 1/n2, the confinement potential in quantum dots can be approximated as a parabolic potential, reminiscent of simple harmonic oscillators, leading to equi-spaced eigen-energies in the quantum dot according to the rules of quantum mechanics. Quantum dot confinement also leads to an increase of the effective band gap, since the lowest eigenstates in the conduction and valence band are pushed up in energy, leading to an increasing blue shift, as dot sizes are reduced. This can lead to a dramatic change in the colors of quantum dots made of a certain semiconductor, simply by changing the dot size, with obvious applications in optoelectronics. For instance, one can incorporate such quantum dots in the active regions of lasers, and tune the emission wavelengths toward the blue, and sharpen the line widths compared to three-dimensional active regions. Quantum dots have also been used in solar cells to engineer the absorption characteristics of the cells, and match it better to the solar spectrum.

Quantum dots can be made by so-called top down approaches involving nanoscale lithography, followed by etching. Alternatively, bottom-up schemes such self-assembled quantum dots can be formed using heteroepitaxy. As described in Section 1, if we grow a dissimilar semiconductor on a substrate, if there is a lattice mismatch, it leads to strain in the epitaxial layer. Generally, the initial layers are smooth, which is known as the layer by-layer Frank-Van der Merwe growth mode. As the layer becomes thicker, often there is roughening of the epitaxial layer because of increasing strain- this is known as the Volmer-Weber growth mode. If the lattice mismatch in the heteroepitaxial system is large, it can lead to very rough morphology or quantum dots forming on the surface of the substrate in a self-assembled fashion. This is known as the Stranski-Krastanov mode, and is the preferred mode of fabrication in many optoelectronic devices where precise location of the dots is not critical. This avoids time-consuming lithography and etching, and allows, for example, inclusion of quantum dots in the cavity of a laser to sharpen the emission line-width.

An interesting electronic application of quantum dots is in flash memories that we discussed in Section 9. Recall that electrons can be stored in a non-volatile fashion in the floating gate of an MOS structure, and the presence or absence of these electrons corresponds to digit bits 1 or 0. As one scales down the sizes of these flash memory cells, it would be desirable to scale down the thicknesses of the tunnel dielectric, in accordance with the scaling laws we discussed. However, one finds that if the tunnel oxide is less than ~8 nm, there are inevitably manufacturing "weakspots" in the oxide which cause the stored electrons to leak away and not be retained for the requisite 10 years or longer. If the continuous floating gate electrode is replaced by an array of discontinuous quantum dots, and electrons are stored in them, we can more aggressively scale down the tunnel oxide, and therefore the memory cell. A weak spot in the tunnel dielectric might discharge electrons in a quantum dot in the vicinity of the weak spot, but the vast majority of the other dots which are electrically discontinuous would still retain the stored electrons. This greatly improves the reliability of the flash memory cells.

7.2 One-Dimensional Quantum Wires

One-dimensional semiconductor quantum wires or nanowires are an attractive platform for making ultra-scaled MOSFETs. These can be viewed as a natural evolution of the FinFETs or MuGFETs that we discussed. Recall that having a gate wrapped around three sides of a channel in a three-dimensional structure gives the gate better electrostatic control of the channel potential compared to a bulk MOSFET, and leads to better channel length scalability. In a nanowire MOSFET, the gate can be wrapped all around the channel, leading to even better gate control than in a FinFET. However, the drive current of an individual nanowire FET is generally low. Hence, one needs to make parallel arrays of these devices.

Just as with quantum dots, such quantum wires can be formed by top down lithography and etching techniques, or by novel bottom up schemes.

One such bottom up scheme is known as the Vapor-Liquid-Solid (VLS) approach, first developed by Wagner in the 1960s. In this scheme, one pat terns metal catalysts such as Au to form quantum dots on a substrate. The structure is then loaded into a chemical vapor deposition system, and appropriate precursor gases are introduced, with the substrate at a high enough temperature that the Au metal catalysts melt. For example, to grow Si nano wires, silane (SiH4) is flowed in such that it dissolves in the molten Au catalyst dots. There is a super saturation of Si in the Au, leading to an extrusion of Si atoms as single crystal Si nanowires growing vertically on top of the Si substrate, with the Au catalyst floating on top of the nanowire. At the end of the VLS growth, the Au catalysts can be etched off. Fortunately, due to the low solid solubility of Au in Si, there is negligible Au contamination of the nanowires or the substrate. Vertical FETs can be made in the forest of nanowires, or these nanowires can be harvested and subsequently laid down flat on another substrate for subsequent device processing. Other precursors such as germane for Ge nanowire growth, or III-V nanowires, can be grown by VLS.

Another type of 1D system is the carbon-based nanotube. As we saw in Section 1, carbon can be tetrahedrally bonded to four other nearest neighbor carbon atoms via sp3 bonding, leading to diamond. But C can also undergo sp2 bonding which leads to a planar structure, such as the sheets of carbon atoms in graphite. This two-dimensional planar bonding arrangement of carbon led to the first nanostructures in C, based on so-called Buckyballs or fullerenes.

[The name buckyball or fullerene is based on the American architect Buckminster Fuller who developed the iconic geodesic dome, which looks similar to these carbon zero-dimensional nanostructures.]

FIG. 18 Nanostructures of carbon: (a) 2-D graphene; (b) 1-D nanotube; (c) 0-D Buckyballs (fullerene); (d) linear band structure of graphene showing Dirac cones.

These are spherical shells of carbon atoms reminiscent of the quantum dots we described in the previous section. Fullerenes can be elongated into a tubular structure, leading to carbon nanotubes [FIG. 18], and FETs can be made in them. These have somewhat similar properties as nanowire FETs, but there are interesting differences in the density of states of these carbon-based materials. For instance, depending on precise angular orientation of the carbon atoms in the cylindrical tube, which is known as the helicity or chirality of the nanotube, they behave as semiconductors (which are good for FETs), or metals (suitable for interconnects).

7.3 Two-Dimensional layered crystals

We have already met two-dimensional systems such as two-dimensional electron gases (2-DEG) in the inversion layer of a MOSFET made in a three dimensional bulk crystal. Such quasi-two-dimensional systems are formed through electrostatic confinement. Recently, there have been breakthroughs in two-dimensional atomic crystals or layered materials.

Staying with the theme of carbon, it was shown by Geim and Novoselov in 2004 that one can peel off individual sheets of sp2-bonded carbon atoms from graphite, leading to two-dimensional atomic crystals called graphene.

One can also view graphene as carbon nanotubes which are sliced along the axis of the cylinder, and flattened out into monoatomic sheets of carbon.

The unit cell of graphene consists of a hexagonal array of carbon atoms with a unique linear band structure, E(k), shown in FIG. 18. This is obviously different from the parabolic E(k) relationship seen in most semiconductors. We saw that the curvature of these parabolic bands determines effective mass of the electrons and holes. By contrast, the linear band structure in graphene is more reminiscent of the linear dispersion relationship of photons, which are known to have zero rest mass, and thus travel at the speed of light, c. The carriers in graphene, in analogy with photons, also have zero effective mass, and are known as massless Dirac fermions, traveling at a group velocity determined by the slope of the E(k) dispersion relationship discussed in Section 1.5. The conical E(k) surfaces are known as Dirac cones. In graphene, electrons and holes travel at a so-called Fermi velocity, which is 10* that of the saturation drift velocity in Si or most semi conductors. Clearly, this makes graphene an attractive platform for very high speed devices such as RF transistors. Unfortunately, one sees from the band structure in FIG. 18d, that there is no band gap between the valence and conduction band. Hence, MOSFETs in graphene have high off-state leak age currents for the reasons discussed in Section 6, making graphene FETs unsuitable for digital logic which demand high ON-OFF ratio.

This has led to interest in other two-dimensional layered materials which are similar to graphene, but have a band gap. One class of such materials are the transition metal dichalcogenides (TMDs). Transition elements include Mo, W, etc. while chalcogens in the periodic table are Column VI elements such as S, Se, and Te. Transition metal dichalcogenides such as MoS2 have a hexagonal unit cell like graphene, and two-dimensional mono-atomic sheet structure, but unlike graphene, have a band gap, making these materials attractive for short channel MOSFETs. One could think of them as SOI scaled to the ultimate limit of atomic layer thicknesses.

Yet another set of two-dimensional layered materials which have garnered interested recently are the topological insulators (TI) such as the bismuth - selenide/telluride. This class of solids are insulating in the bulk, but have Dirac cone metallic surface states, similar to graphene, but with a novel twist. Remember that electrons have a quantum number called spin, which can have values of {½, corresponding to spin "up" or "down." Normally, in most semiconductor devices we have equal populations of both spins.

The spin simply adds a factor of 2 in the density of states, but otherwise can be ignored. When electrons orbit around the nucleus, they see an effective magnetic field due to the orbital motion, and spin up/down electrons can have slightly different energies in this magnetic field. (The split-off bands are the result of such interactions.) On TI surfaces such as Bi2Se3, due to strong spin-orbit interactions in heavy nuclei such as Bi, the spin of the electron is locked orthogonally to the wavevector k, which determines its orbital motion. In other words, if electrons moving to the left on the TI surface have spin up, electrons moving to the right will have spin down. Such intriguing physics may lead to novel nanoelectronic devices in the future which will not only exploit the charge of the electron, but also its spin, a nascent field dubbed spintronics, in analogy with electronics.

7.4 Spintronic memory

Although spintronics based on semiconductors is a burgeoning field, spin based ferromagnetic devices have been used for a long time in hard disks, and more recently in spin transfer torque random access memory (STTRAM). A brief discussion of ferromagnetism in solids is warranted to explain these devices. Spinning electrons can be thought of as tiny, atomic magnets which point up or down. Ferromagnetism is a magnetic state where a majority of the electron spins point one way or the other, even without an applied external magnetic field (which would tend to orient the electron spins.) As we have mentioned in Section 7.3, normally in solids spin up/down electrons are equally likely to be found, and the density of states has a factor of 2 spin degeneracy. We also saw in Section 3 that electrons, being fermions, must have an overall wavefunction e(r, s), depending on position, r, and spin, s, that is anti-symmetric. So, if the spatial part of the wavefunction is symmetric, the spins are anti-parallel, and vice versa. So, in this case, since the symmetric (bonding) orbital is the lower energy state, it is energetically favorable for spins to be anti-parallel, and the solid is not ferromagnetic. Such solids are paramagnetic, with no permanent magnetism.

On the other hand, if free electrons are considered, which are not subjected to a strong ion core potential, the anti-symmetric orbital (with parallel spins) is energetically favorable because the electrons are further apart on average and, therefore, there is less Coulomb repulsion. Since the spins are parallel, it leads to ferromagnetism. So, what aligns the spinning electrons in a ferromagnet is electrostatic Coulomb interactions, rather than the much weaker magnetostatic interactions between the magnetic dipoles.

This larger effective field is known as the Weiss exchange field (because it is driven by the anti-symmetry of electron wavefunctions when two electrons are interchanged). As a result, in a ferromagnet, there is a higher of density of states of the majority spins near the Fermi level (FIG. 19a).

FIG. 19 (a) Spin-based memory. Depending on whether the "free" magnet on the right is parallel (anti-parallel) to the "fixed" magnet on the left, we have a low (high) tunneling resistance corresponding to the two memory states. (b) Phase change memory whose resistance changes depending on the crystallinity of the chalcogenide.

This is the basis of a host of ferromagnetic spin-based memories. For example, one can have a permanent fixed ferromagnet that always points up, separated by a tunnel dielectric from a free magnet which can point up or down. If the two magnets are aligned, there is a high density of initial states and final states for majority spin electron tunneling near the Fermi level. This corresponds to a low tunnel resistance, and could correspond to bit 1. (Spins do not flip during the tunneling process.) On the other hand, if the free magnet is anti-parallel to the fixed magnet, there is a mismatch between the initial and final density of states for both types of spin, and the tunnel resistance will be higher, corresponding to bit 0. This is known as tunnel magnetoresistance (TMR). This, and similar effects such as giant magnetoresistance (GMR), are used in hard disk memories that are ubiquitous in computers.

These effects are also the basis of STTRAMs which offer a new type of "universal" memory that might one day supplant all the other types of memory that we discussed in Section 9 (SRAM, DRAM, flash). In STTRAMs, to write a bit 1, a current flows through the fixed magnet, which spin polarizes the electrons along the majority spin direction. When an electron tunnels into the free magnet, it transfers spin angular momentum to the free magnet, applies a torque, and flips it to make it parallel to the fixed magnet. This sets the STTRAM in the low resistance state (bit 1) during read operation. If the polarity of the write current is reversed, the sign of the angular momentum transfer to the free magnet is flipped, and it becomes anti-parallel to the fixed magnet, setting it into the high resistance state (bit 0).

7.5 Nanoelectronic resistive memory

As we saw for STTRAMs, memory devices can be based on two resistance states, corresponding to digital bits 1 and 0. In some sense, such memory devices are simpler to make than logic transistors, where requirements, such as ON-OFF ratios, etc., are much more stringent. In recent years, novel non volatile memories have been developed based on resistance changes. In resistive RAMs (ReRAMs), a dielectric such as high-k dielectric is sandwiched between two metal electrodes. Flowing a high write tunneling current through the dielectric can create defect trap states or charges in the dielectric, which can modify its resistance. The phenomena are akin to what we discussed in the context of I-V characteristics of SiO2. The precise details of programming (called setting) and erase (re-setting) depend on the dielectric used in ReRAMs, and the physics is still somewhat controversial. In titanium oxide-based dielectrics, it is believed that the mechanism involves creation and annihilation of a string of oxygen vacancies, which results in a resistance change. Some dielectrics can be set and reset with unipolar pulses of different amplitude, whereas others require bipolar pulses of opposite polarity. Resistive RAMs are also known by a colorful name, Memory Resistor or memristor.

Typical changes in resistance in ReRAM are several hundred percent. The challenge in these devices is demonstrating reliability in terms of repeated cycling between the two resistance states, without suffering from TDDB.

Another type of resistive memory, where the resistance difference between states 0 and 1 is much higher than in ReRAM (factors of ~10^5 are typical), is the phase change memory (PCM) (FIG. 19b). Here the memory storage element is a glassy material, perhaps a chalcogenide such as Ge2Sb2Te5 (GST). The passage of an electric current through a heating element such as TiN is used to quickly heat and quench the GST, making it amorphous, which is a high resistance phase. Alternatively, it can be held in its crystallization temperature range for some time, thereby switching it to a low resistance crystalline state. Interestingly, phase change materials are not a new idea. They have been used extensively in rewriteable RW compact discs (CDs) as the storage medium. A laser makes the layer amorphous (low reflectivity) or polycrystalline (high reflectivity) for optical storage of the digital bits.

The field of nanoelectronics is still in its infancy. As the great Richard Feynman said, "There is plenty of room at the bottom!"


1. High frequencies in the microwave regime can be obtained by negative differential resistance achievable by tunneling (Esaki diodes), transferred-electron effects (Gunn diodes), or transit-time effects (IMPATT diodes).

2. High power switching is possible with p-n-p-n diodes, thyristors, or SCRs. These devices can be understood in terms of two coupled BJTs. Similar effects in CMOS cause latchup.

3. Modern power devices are based on the IGBT, which is a combination of an SCR and a MOSFET.

4. Nanoelectronics is based on the mesoscale between the larger (microscale) and smaller (atomic) dimensions where novel phenomena can be beneficially exploited.


1. Sketch the band diagram for an abrupt junction in which the doping on the p side is degenerate and the Fermi level on the n side is aligned with the bottom of the conduction band. Draw the forward- and reverse-bias band diagrams and sketch the I-V characteristic. This diode is often called a backward diode. Can you explain why?

2. What determines the peak tunneling voltage Vp of a tunnel diode? Explain.

If a large density of trapping centers is present in a tunnel diode (Fig. P10-2), tunneling can occur from the n-side conduction band to the trapping level (A-B). Then the electrons may drop to the valence band on the p side (B-C), thereby completing a two-step process of charge transport across the junction. In fact, if the density of trapping centers is large, it is possible to observe an increase in current as the states below EFn pass by the trapping level with increased bias. In Fig. P10-2, the trapping level Et is located 0.3 eV above the valence band. Assume that Eg = 1 eV, EFn - Ec on the n side equals Ev - EFp on the p side, and both EFn - Ec and Ev - EFp equal 0.1 eV.

(a) Calculate the minimum forward bias at which tunneling through Et occurs.

(b) Calculate the maximum forward bias for tunneling via Et.

(c) Sketch the I-V curve for this tunnel diode. Assume that the maximum tunneling current via Et is about one-third of the peak band-to-band tunneling current.

3. (a) Write down the complete continuity equation and solve it. Find the excess minority hole concentration as a function of time (t) for t Ú 0. Assume that there is no applied field but recombination is present. Consider an n-type Si sample with donor concentration as 10^16 /cm^3 at T = 300 K. Due to uniform illumination of light at t = 0, EHPs are generated at a rate of 10^20 /cm^3. If minority carrier lifetime is 10 nsec, find the excess hole concentration at t = 5 msec.

(b) When the steady state excess hole concentration is 2 * 10^14 /cm^3 as ti 8, estimate the minority carrier lifetime

(c) Determine the time at which the excess minority carrier concentration becomes one third of the steady state value obtained in part (b).

4. Assuming that nG electrons/cm^3 are in the lower (central) valley of the GaAs conduction band at time t and nL are in the satellite (L) valleys, show that the criterion for negative differential conductivity (dJ/dE 6 0) is where oG and oL are the electron mobilities in the G and L valleys, respectively.

(Note: n0 = nG + nL.) Discuss the conditions for negative differential conductivity, assuming that the mobilities are approximately proportional to E-1.

5. We wish to estimate the d-c power dissipated in a GaAs Gunn diode. Assume that the diode is 5 um long and operates in the stable domain mode.

(a) What is the minimum electron concentration n0? What is the time between current pulses?

(b) Using data from FIG. 9a, calculate the power dissipated in the sample per unit volume when it is biased just below threshold if n0 is chosen from the calculation of part (a). In general, does operation at a higher frequency result in greater power dissipation?

6. (a) Calculate the ratio NL/NG of the effective density of states in the upper (L) valleys to the effective density of states in the lower (G) valley of the GaAs conduction band (FIG. 6).

(b) Assuming a Boltzmann distribution nL/nG = (NL/NG) exp(-?E/kT), calculate the ratio of the concentration of conduction-band electrons in the upper valley to the concentration in the central valley in equilibrium at 300 K.

(c) As a rough calculation, assume that an electron at the bottom of the central valley has kinetic energy kT. After it is promoted to the satellite (L) valley, what is its approximate equivalent temperature?

7. Explain why two separate transistors cannot be connected as in FIG. 11 to achieve the p-n-p-n switching action of FIG. 10.

8. In the p-n-p-n diode (FIG. 12a), the junction j3 is forward biased during the forward-blocking state. Why, then, does the forward bias provided by the gate to-cathode voltage in FIG. 13 cause switching?

9. (a) Sketch the energy-band diagrams for the p-n-p-n diode in equilibrium, in the forward-blocking state, and in the forward-conducting state.

(b) Sketch the excess minority carrier distributions in regions n1 and p2 when the p-n-p-n diode is in the forward-conducting state.

10. Use schematic techniques such as those illustrated in Fig. 7-3 to describe the hole flow and electron flow in a p-n-p-n diode for the forward-blocking state and for the forward-conducting state. Explain the diagrams and be careful to define any new symbols (e.g., those representing EHP generation and recombination).

11. In a coupled transistor model in presence of avalanche multiplication, the multiplication factor for the electrons is two times larger than that for the holes.

The emitter to collector current transfer ratio and the collector saturation current for the n-p-n transistor is four times than that for the p-n-p transistor. Find the expression for the total current flowing through the device.


Study the ITRS roadmap section on Emerging Research Devices. This has projections about next-generation CMOS devices as well as novel devices using nanotechnology.

• Write a report on which of these devices you think will be used in products in the next 5 years, 10 years, and 20 years.

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