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As switching frequencies increase, it becomes of paramount importance to reduce the switching losses in the converter. These are the losses associated with the transition of the switch from its on-state to off-state, and back. The higher the switching frequency, the greater the number of times the switch changes state per second. Therefore, these losses are proportional to the switching frequency. Further, of these frequency-dependent loss terms, the most significant are usually those that take place within the switch itself.
Therefore, understanding the underlying sequence of events in the switch during each transition, and thereby quantifying the losses associated with each of these events, has become a key expectation of any power supply designer.
In this section, we are going to focus mainly on the mosfet, since that's the most widely accepted "switch" in most high-frequency designs today. We will split its turn-on and turn-off transitions into small well-defined subintervals, and explain what happens in each of these. The associated design equations will also be presented. Note however, that as in most related literature, we too will be resorting to certain simplifications, since modeling the mosfet (and its interplay with the board that it's mounted on) is certainly not a trivial task, to say the least. As a result, it's possible that theoretical estimates can end up underestimating the actual switching losses by a large margin (typically 20 to 50%). The designer should keep that in mind, and may need to eventually incorporate some sort of a "fudge factor," to correspond with reality. However, in our analysis, we have included a "scaling factor" to try and minimize this error.
We will also show how to estimate driver requirements, and demonstrate the importance of correctly matching driver capability to the mosfet in a given application. That should ultimately help not only applications engineers to pick better mosfets for their applications, but also IC designers involved in the process of designing driver stages for target applications.
A cautionary note with regard to the terminology - in most of our switching analysis, what we are calling the "load" is the load as seen by the transistor - it's not the load of the dc-dc converter stage. Similarly the "input voltage" is only the voltage across the mosfet when it's OFF - it's not the input to the dc-dc converter stage. We will eventually make the required connections into the area of power conversion, but it should be clear that initially at least, the discussion is more from the standpoint of the mosfet, not the topology that it may be a part of.
Switching a Resistive Load
Before we take up inductors, it's instructive to first understand what happens when we switch a resistive load.
For simplicity, we are considering an ideal situation. So we start with a "perfect" n-channel mosfet in Ill. 1. It behaves in the following manner ++ It has zero on-resistance.
++ With zero gate-to-source voltage "Vgs" applied at its gate, it's completely non-conducting.
++ As we raise the gate-to-source voltage Vgs slightly above ground, it starts conducting, and so a drain current 'Id' flows from the drain to the source terminal.
++ The ratio of the drain current to the gate voltage is defined as the transconductance 'g' of the mosfet. It is expressed in 'mhos,' that's , ohm spelled backward. Nowadays however, mhos is being increasingly called Siemens, or 'S.'
++ We are assuming that g is a constant -- equal to 1sec for this particular mosfet. So for example, if we apply 1 V at the gate, the mosfet will pass 1 A. If we apply 2 V, it will pass 2 A, and so on.
Ill. 1: Switching a Resistive Load
The application circuit shown in Ill. 1 works as follows:
++ The applied input voltage is 10 V.
++ The external resistance (in series with the drain) is 1 ohm.
++ The gate voltage is ramped up linearly with respect to time. So at t = 1s it's 1V, at t = 2s it's at 2V, at t = 3s it's at 3V, and soon.
The analysis proceeds as follows ("Vds" is the drain-to-source voltage at any given moment, "Vgs" is the gate-to-source voltage, and "Id" is the drain-to-source current):
++ At t = 0, Vgs equals 0 V. Therefore, from the transconductance equation, Id is 0 A.
So the drop across the 1-ohm resistor is 0 V (using Ohm's law). Therefore the voltage at the drain of the mosfet, 'Vds,' equals 10 V.
++ At t = 1 s, Vgs equals 1. Therefore from the transconductance equation, Id is 1 A.
So the drop across the 1-ohm resistor is 1 V (using Ohm's law). Therefore Vds equals 10 - 1 = 9V.
++ At t = 2 s, Vgs equals 2. Therefore from the transconductance equation, Id is 2 A.
So the drop across the 1-ohm resistor is 2 V (using Ohm's law). Therefore Vds equals 10 - 2 = 8V.
We proceed ramping up the gate voltage progressively in this manner. When 10 s have elapsed, Vgs is 10 V, Id is 10 A, and Vds is 0 V. After 10 s, no further change in Vds or Id can occur, even if Vgs is increased further.
Note: In general, if the gate voltage is increased beyond what it takes to deliver a specified maximum load current, we say that in effect, we are applying "overdrive." This is usually considered wasteful in that sense, but in practice, overdrive helps reduce the on-resistance of the mosfet, and thereby decrease its conduction losses.
Ill. 2: The Voltage and Current Waveforms when Switching a Resistive Load
The maximum load current in our example is therefore 10 A, and is "Id_max" in Ill. 2.
If we plot the drain current and drain voltage with respect to time, we see that the crossover time, 'tcross,' is 10 s here. Note that this time is by definition the time for both the voltage and the current to complete their transitions.
The energy lost in the mosfet during the transition is
E = Integral (tcross to 0) Vd(t)Id(t)dt Joules
A conceptual point to keep in mind here is that in related literature, it's often stated (rather inaccurately as we will see) that the "area (jointly) enclosed by the voltage, current, and the time axis is the energy lost in the switch" (during the transition). This is the gray isosceles triangle in Ill. 2. Half of this gray area has been hatched. We thus see that within the "crossover interval rectangle," there are eight triangles (in all) with the same area as the hatched triangle. Therefore the total gray area is one-fourth the area of the crossover interval rectangle. So if the statement about energy being equal to the enclosed area is true, we would have gotten
E = 1/4 · Vin · Id_max · tcross Joules
This isn't correct. In fact, we would have reached the same unfortunate conclusion had we argued on the grounds that during the crossover duration, the average voltage is V_in/2 and the average current is Idmax/2, and therefore the average cross-product is equal to (V_in × Id_max)/4. This is fallacious too. In general,
A_AVG × BAVG = _ A × B _ AVG
So yes, this could in fact have turned out to be true, if, while the voltage was falling, the current had remained fixed, and vice versa. That is what happens with an inductive load, as we will soon see. However, in the case of a resistive load, both the voltage and the current change simultaneously during the crossover interval. We clearly need another (better) way to calculate the switching loss for the resistive case.
Ill. 3: The Instantaneous Energy Dissipation Curve for Resistive Switching
Let us compute the instantaneous cross-product Vds(t) × Id(t) at t = 1, 2, 3, 4 ... seconds.
If we plot these points out, we get the bell-shaped curve shown in Ill. 3. So, to get the energy lost during the crossover, we need to find the net area under this curve. But we can see that isn't going to be easy, because this curve is rather oddly shaped. In fact, there is no other way than to carry out a formal integration/summation procedure. And for that we have to revert to the basic equations for voltage and the current (as presented in Ill. 1).
We then integrate their product over time, and we get:
E = 1/6 · Vin · Id_max · tcross Joules
This is the correct result for the energy lost in the switch, during a resistive turn-on transition.
If we now turn the mosfet OFF in the same way (with the crossover time kept fixed), we will get exactly the same energy loss term again, though this time with the voltage rising and the current falling.
We can thus also conclude that if we switch repetitively at the rate of fsw Hz, the net dissipation, that's , total energy lost per unit time as heat, is equal to
Psw = 1/3 · Vin · Id_max · tcross · fsw Watts
This is therefore the switching loss (in the switch) for the case of a resistive load.
Note: Note that to be precise, this particular term more correctly should be called the 'crossover loss,' as was first pointed out in Section 1. The crossover loss (i.e. specifically attributable to the V-I overlap) isn't necessarily the entire switching loss taking place in the switch, as we will see.
Now, suppose we had ramped up the gate voltage at a rate of 1 V per second as before, but ramped down faster, say, at the rate of 2 V per second. Then the turn-on time and the turn-off transition times would be different. So in that case we need to split up the crossover loss 'Psw' as follows:
Psw = P_turnon + P_turnoff
where 'tcrosson' and 'tcrossoff ' are the crossover times during turn-on and turn-off respectively.
Now suppose the value of the external resistor was made larger, say 2 ohms instead of 1 ohm. Then the voltage at the drain would have swung from 10 V to 0 V in only 5 s. And by that time, the drain current would have reached only 5 A. The gate voltage would at that moment be only at 5 V. However, no further change in Id is possible (even if we increase Vgs further). Therefore, though the crossover interval has become half of what it was, the rise time of the current is still equal to the fall time of the voltage (i.e. 5 s). This is a characteristic only of resistive loads (since V = IR applies to them).
The rules of the game change considerably, when we have an inductive load. In fact the calculation becomes simpler - ironically because the simplicity (and predictability) of Ohm's law is lost.
Switching an Inductive Load
When we switch an inductive load (with a freewheeling path present of course!), we will get the waveforms shown in Ill. 4 (idealized). At first sight they may seem similar to the resistive load waveforms of Ill. 2. But on closer examination, they are very different.
In particular, we see that when the current is swinging, the voltage remains fixed, and when the voltage is swinging, the current remains fixed.
Let us calculate the crossover loss under these conditions. We can do a formal integration as before. But this time, we realize there is in fact an easy way out! Since one of the parameters (V or I) is fixed when the other is varying, we can now justifiably take the average value of the current, Id_max/2, and the average value of the voltage, V_in/2, to find the average cross-product. In this manner, we arrive at the energy lost (in Joules) during the turn-on transition
Ill. 4: The Voltage and Current Waveforms when Switching an Inductive Load
Ill. 5: Analyzing the Transitions in a Buck Converter
Note that for the same reason as indicated above, we can now justifiably think in terms of the area enclosed. By simple geometry, the gray area in Ill. 4 is half the rectangular area, and so we get the same result as above.
We realize that our ability to avoid integration (and use simpler arguments to calculate the crossover loss) is just a piece of "good luck" here - specific to the case of an inductive load.
Finally, when we switch repetitively, the inductive switching loss is
Psw = Vin · Id_max · t_cross · fsw Watts
Note: We may superficially conclude that switching an inductive load leads to a dissipation three times greater than a resistive load. That is indeed true, but only under the exact same conditions. In reality, the value of Id_max is fixed for the case of a resistive load (depending on the value of the resistance used). But for an inductive load, the current can be virtually anything - there is no set "Id_max" as such anymore - it's whatever current that happens to be flowing through the inductor at the instant of switching (either just before or after).
A basic question still remains: why are the inductive waveforms so different from the resistive case? To answer that, we have go back to our previous analysis of the resistive load case. There we will see that we had invoked Ohm's law to find the voltage across the switch.
But with an inductor, Ohm's law clearly does not apply. So to get the waveforms shown in Ill. 4, we have to recollect something we learned in Section 1 - when we turn the switch OFF, the inductor will create whatever voltage is necessary to maintain the continuity of current through it. Let us now show this principle at work in an actual buck converter, for example (see Ill. 5).
In Ill. 5, we first consider the turn-on transition (on the left). Just prior to this, the diode is obviously carrying the full inductor current (circled "1"). Then the switch starts to turn ON, trying to share some of this inductor current (circled "2"). The diode current therefore must fall correspondingly (circled "3"). However, the important point is that while the switch current is still in transit, the diode has to be able to pass some current (the remainder, or leftover amount of the inductor current). But, to provide even some of the inductor current, the diode must remain fully forward-biased. Therefore, nature (i.e. induced voltage in this case) forces the voltage at the switching node to remain slightly below ground –so as to keep the anode of the diode about 0.5 V higher than the cathode (circled "4"). Then, by Kirchhoff's voltage law, the voltage across the switch stays high (circled "5"). Only finally, when the entire inductor current has shifted to the switch, does the diode "let go." With that, the switching node is released, and it flies up close to the input voltage (circled "6") - and so now, the voltage across the switch is allowed to fall (circled "7").
++ We therefore see that at turn-on, the voltage across the switch does not change until the current waveform has completed its transition. We thus get a significant V-I overlap.
If we do a similar analysis for the turn-off transition (right side of Ill. 5), we will see that for the switch current to start decreasing by even a small amount, the diode must first be "positioned" to take up any current coming its way. So the voltage at the switching node must first fall close to zero, so as to forward-bias the diode. That also means the voltage across the switch must first transit fully, before the switch current is even allowed to decrease slightly (see Ill. 5).
++ We therefore see that at turn-off, the current through the switch does not change until the voltage waveform has completed its transition. We thus get a significant V-I overlap.
We see that the fundamental properties and behavior of an inductor, as described in Section 1, are ultimately responsible for the significant V-I overlap during crossover.
The same situation is present in the case of any switching topology. Therefore, the switching loss equation presented earlier also applies to all topologies. What we have to remember is, that in our equations, we are referring to the voltage across the switch (when it's OFF), and the current through it (when it's ON). In an actual converter, we will need to ultimately relate these V and I to the actual input/output rails and load current of the application. The procedure for that's described later.
Switching Losses and Conduction Loss
The underlying motivation for initiating switching in modern power conversion is often simplistically stated as follows - by switching the transistor, either the voltage across the transistor is close to zero, or the current through it's close to zero, and therefore the dissipation cross-product "V × I" is also almost zero. We have seen that during the transition, that doesn't really hold true anymore (the V-I overlap). Similarly, we should keep in mind that though the V × I losses are much closer to the ideal or "expected" value of zero when the switch is OFF, there are considerable losses when the switch is ON. That is because when the switch is OFF, it's really so - the leakage current through a modern semiconductor switch is almost negligible. However, when the switch is ON, the voltage across it's not even close to zero in many cases. One of the highest reported forward drops is in the "Topswitch" (an integrated switcher IC meant for medium off-line flyback applications) - over 15 V (over rated current and temperature)! In general, there will remain a significant V × I loss term even after the inductor current has shifted entirely from the diode to the switch. This particular loss term is clearly the conduction loss, P_COND (of the switch). It can in fact be comparable to, or even greater than, the crossover loss.
However, unlike the crossover loss, the conduction loss isn't frequency-dependent. It does depend on duty-cycle, but not on frequency. E.g., suppose the duty cycle is 0.6; then in a measurement interval of say, one second, the net time spent by the switch in the ON-state is equal to 0.6 seconds. But we know that conduction loss is incurred only when the switch is ON. So in this case, it's equal to a × 0.6, where "a" is an arbitrary proportionality constant. Now suppose the frequency is doubled. Then the net time spent in the on-state (in 1 second) is still 0.6 seconds. So the conduction loss remains a × 0.6. But now, suppose the duty cycle changes from 0.6 to 0.4 (the frequency can be even doubled in the process), the conduction loss is reduced to a × 0.4. So we realize that conduction loss can't possibly depend on frequency, only on duty cycle.
We can pose a rather philosophical question - why is it that the switching loss is frequency-dependent, but not the conduction loss? That is simply because the conduction loss coincides with the interval in which power is being processed in the converter. Therefore, as long as the application conditions don't change (duty cycle fixed, input and output power fixed), neither can the conduction loss.
The equation to calculate the conduction loss of a mosfet is simply:
P_COND = I_RMS^2 × Rds Watts
where 'Rds' is the on-resistance of the mosfet. IRMS is the RMS of the switch current waveform. It is equal to
I_RMS = I_O ×
where IO is now the load current of the dc-dc converter stage, and D is its duty cycle. Note that to a first approximation (current ripple ratio assumed very small), this is equal to
IRMS ˜ IDC × v D (buck, boost, and buck-boost)
where IDC is the average inductor current and 'IRMS' is the RMS of the switch current waveform.
The diode conduction loss is the other major conduction loss term in a power supply. It is equal to VD × ID_AVG, where VD is the diode forward-drop. IDAVG is the average current through the diode -- equal to IO for the boost and the buck-boost, and I_O × (1 - D) for the buck. It too is frequency-independent.
We realize that the way to reduce conduction losses is by lowering the forward-drops across the diode and switch. So we look for diodes with a low drop -- like the Schottky diode.
Similarly, we look for mosfets with a low on-resistance "Rds." However, there are compromises involved here. The leakage current in a Schottky diode can become significant as we try to choose diodes with very low drops. We can also run into significant body capacitance, which will end up being more dissipative. Similarly, the speed at which the mosfet switches can be adversely affected as we try to reduce its Rds.
A Simplified Model of the Mosfet for Studying Inductive Switching Losses
In Ill. 6, on the left, we have the basic (simplified) model of the mosfet. In particular, we observe that it has three parasitic capacitances - between its drain, source, and gate.
These "small" inter-electrode capacitances are the key to maximizing switcher efficiency, especially at higher switching frequencies. Their role in the switching transition needs to be understood clearly.
We have seen that the basic reason why we get any crossover loss in the first place is because there is an unavoidable V-I overlap during every switching transition. That overlap occurs because the inductor keeps trying to force current, and tries to create suitable conditions for that to happen seamlessly, as we switch. But the reason why this overlap lasts as long as it does is mainly because these three inter-electrode capacitors are demanding to be charged or discharged (as the case may be) at every switching event - so that they can reach their new dc levels, commensurate with the altered state of the switch. So crudely stated, if these capacitances are "big," they take a longer time to charge or discharge, thus increasing the crossover (overlap) time. And that in turn increases the crossover loss.
Further, since the charging and discharging paths of these capacitors often include the gate resistor, the value of the gate resistance also considerably impacts the transition time, and thereby the switching loss.
Ill. 6: Simplified Model of Mosfet
On the right side of Ill. 6, we have further simplified our simple model. So we have lumped the internal and external inductances present at the drain into a single leakage inductance "L_lk." Note that we are ignoring any gate-to-source inductance, thus implicitly assuming the PCB layout is very good in this regard. We also lump the small resistor present internally inside the mosfet, along with the external gate resistor (if present), and the driver resistance (its internal pull-up or pull-down) - to give a single effective 'R_drive,' or drive resistance.
Note that in Ill. 6, the main inductor is "coupled" - because it has a freewheeling path available. But the leakage (or parasitic) inductance is "uncoupled," because it has no path to send forth its energy. It therefore expectedly "complains" - in the form of a voltage spike (whenever we try to change the current through it). However, in our analysis, we will be assuming this leakage inductance is very small (though not necessarily negligible either). We will find that this results in certain artifacts in the switching waveforms, which makes them appear slightly different, as compared to the idealized inductive switching waveforms shown in Ill. 4 and Ill. 5. However, it turns out that these artifacts are mainly of academic interest (provided of course that R_drive is "small"). In addition, the artifacts in question typically help decrease the crossover losses slightly. Therefore, the idealized waveforms are more "conservative" in that sense, and we would do well just sticking to them.
Turning our attention to the "circuit" shown in Ill. 6, we should be clear that this circuit doesn't really work! We know from our discussions in Section 1 that we can never hope to achieve a steady state without at least an output capacitor present - to charge up and thereby help stabilize the volt-seconds across the inductor. So this circuit's clearly an idealization - it only helps us to perform a paper-analysis of a particular switching transition.
Note that ultimately, the switch cares only about the voltage that appears across it when it turns OFF, and the current passing through it when it's ON. That is why this simple circuit can be safely accepted as representative of what happens in any topology, at the moment of transition. For instance, we could take both the leakage and the main inductor in Ill. 6, and place them on the source-side of the mosfet instead. As long as the gate drive is still well coupled to the source (i.e. no inductance between gate and source), nothing really changes. That is no surprise, because we know that if a certain component (or circuit block)
"A" is in series with "B," we can always interchange their positions and make B in series with A, without changing a thing.
Finally, we should keep in mind that what we are calling the "drain" in our analysis isn't necessarily the pin of the package (of the same name). Nor the switching node! The inductance L_lk separates these points as indicated in Ill. 6. Therefore, for example, though the switching node is necessarily clamped close to the "Vin" rail when the diode is freewheeling, the drain of the device may momentarily show a slightly different voltage (clearly equal to the voltage appearing across L_lk).
The Parasitic Capacitances Expressed in an Alternate System
We will now progress to a detailed study of the inductive switching transitions of a mosfet.
For that, we will be splitting up the turn-on and turn-off into several subintervals of interest.
We will learn that for most of these subintervals, the gate behaves as a simple input capacitance - that's being charged (or discharged) through the resistor 'R_drive.' The situation is identical to the simple RC circuit we discussed in Section 1. In effect, the gate is "blind" to what all may be happening between drain and source (on account of the transconductance of the mosfet).
If we look into the gate, from the viewpoint of the ac drive signal, the effective input charging capacitance is the parallel combination (arithmetic sum) of Cgs and Cgd. We are going to call this simply the gate or input capacitance 'Cg' in our discussion. So
Cg = Cgs + Cgd
The time constant of the charging/discharge cycles of the gate is therefore:
Tg = R_drive × Cg
Note: Here we seem to be indirectly suggesting that the drive resistance is the same for turn-on and turn-off. That need not be so. All the equations we will present can easily take any existing difference in the turn-on and turn-off drive resistances into account. So in general, we will have different crossover times for the turn-on and turn-off transitions. Also note, that in general, within a certain crossover interval (turn-on or turn-off), the actual time it takes for the voltage to transit need not be the same as the time the current takes (unlike the case of a resistive load).
An alternative system of writing the capacitances is in terms of the effective input, output, and reverse transfer capacitances - that's , Ciss, Crss, and Coss respectively. These are related to the interelectrode capacitances as follows:
Ciss = Cgs + Cgd = Cg Coss = Cds + Cgd Crss = Cgd
So we can also write:
Cgd = Crss Cgs = Ciss - Crss Cds = Coss - Crss
In most vendors' datasheets, we can usually find Ciss, Coss, and Crss under the section "typical performance curves." We will then see that these parasitic capacitances are a function of voltage. Clearly, that can significantly complicate any analysis. So as an approximation, we are going to assume that the inter-electrode capacitances are all constants.
We will consult the typical performance curves of the mosfet, and then pick the value of the capacitance corresponding to the voltage that appears across the mosfet when it's OFF (in our given application). Later, we will show how to minimize this error, by the use of a certain "scaling factor."
Gate Threshold Voltage
The "perfect mosfet" we talked about earlier (Ill. 1) started conducting the moment we raised the gate voltage above ground (i.e. source). But an actual mosfet has a certain gate threshold voltage 'Vt.' This is typically 1 to 3 Volts for 'logic-level' mosfets, and about 3 to 5 Volts for high-voltage mosfets. So basically, we have to exceed the stated threshold voltage to get the mosfet to conduct at all ("conduction" defined typically as a current in excess of 1 mA).
Ill. 7: First Interval of Turn-on Ill. 8: Second Interval of Turn-on
Because Vt isn't zero, the definition of transconductance also needs to be modified slightly from
Note that in our analysis, we are making another simplifying assumption -- that the transconductance too is a constant.
Finally, with all this background information, we can start looking closely at what actually happens during the turn-on and turn-off transitions.
Ill. 9: Third Interval of Turn-on
Ill. 10: Fourth Interval of Turn-on The Turn-on Transition
We have divided this interval into four subintervals as detailed individually in Ill. 7 through 10. For quick reference and ease of understanding, the relevant explanations and comments for each sub-interval are also provided within their respective figures.
Briefly, the interval t1 is just the time to get to the threshold Vt. During this time, we just have a simple RC charging circuit. In t2 also, the exponential rise continues, but this time, the drain current starts ramping up. But for all practical purposes, the gate doesn't "know" anything has changed, because the transconductance is fully responsible for the drain current (and further, there is no change in the drain voltage). But in t3, the diode is allowed to stop conducting (since all the inductor current has by now shifted over into the switch). So now the drain voltage swings. But in doing so, it injects a current through Cgd. Note that this capacitance, despite being usually rather small, has probably the greatest effect on the crossover time - because of the fact that it directly injects current from a high switching voltage node (drain) on to the gate. Just prior to the interval t3, Cgd has a relatively high voltage across it. But when the switch is fully ON, the voltage across Cgd must decrease to its new final low value. Therefore, during t3, Cgd is essentially discharging. So the question is - what is the path the Cgd discharge current takes? We can analyze that as follows - having reached the gate, this discharge current has two choices - either to go through Cgs and /or through R_drive. But the gate is already at the constant level of Vt +Io/g - that being the gate voltage level required by the mosfet to support the full inductor current Io. So, to a first approximation, the voltage across Cgs (gate voltage) need not, and does not change. And further, since the general equation for the current through any capacitor is I = CdV/dt, the current through Cgs must be zero, because there is no change in the voltage across it during this sub-interval. Therefore we conclude that all the current coming through Cgd into the gate node gets diverted through R_drive! But the voltage across R_drive is fixed - one end of it's at V_drive, the other at Vt + Io/g. Therefore the current through it's predetermined by Ohm's law. Which means that R_drive is actually in full control of the current through Cgd during the interval t3. However, the current through Cgd also obeys the equation I = C × dV/dt. So if I is fixed at a certain value (by R_drive), we can calculate the corresponding dV/dt across Cgd, and thereby calculate Vd. In effect, this means that Cgd and R_drive are together determining the rate of fall of drain voltage during t3 (and thus the transition time of the voltage). The plateau in the gate voltage waveform during t3 is called the 'Miller plateau'- referring to the effect of the reverse transfer capacitance Cgd. Finally, after the voltage too has completed its swing, the current through Cgd stops completely, and so once again, the gate behaves as a simple RC charging circuit. Note that during t4, the gate is in effect being overdriven - there is no change in the drain current anymore (which is already at its maximum possible value). However, driver dissipation continues during t4.
The 'crossover time,' being the time during which both the current and voltage are transiting, is t2 + t3. As indicated, to know the driver dissipation, we need to consider the entire duration t1 + t2 + t3 + t4. Note that by definition, at the end of t4, the gate voltage is at 90% of its asymptotic level (V_drive). So we can safely assume that for all practical purposes, the driver does very little after this point. Therefore, at the end of t4, the transition is considered complete - from the viewpoint of the switch, and also the driver.
Ill. 11: First Interval of Turn-off
The Turn-off Transition
In a similar manner as for turn-on, we have divided the turn-off interval into four subintervals, as shown in Ill. 11 through 14.
Ill. 12: Second Interval of Turn-off
Briefly, the interval T1 is the time for the "overdrive" to cease; that's , the gate returns to the sustaining level Vt + Io/g (the minimum gate voltage required to support the full drain current Io). During this time, there is no change in the drain current, nor in the drain voltage, and so in effect we once again have a simple RC discharging circuit. In T2, the gate voltage again plateaus. The reason for that's that the drain voltage must first swing close to Vin, and thereby "position" the diode to get forward-biased and be ready to start taking up the current that the switch will progressively shed (see Ill. 5). So T2 is the time for the voltage transition to complete. During T1 and T2 therefore, no change in the drain current occurs.
And with logic similar to what we presented for the turn-on sub-interval t3, during T2 the rate of rise of the voltage Vds is once again determined (only) by R_drive and Cgd. Finally, in T3, the current starts falling toward zero. The gate voltage falls exponentially (as an RC circuit) - down to Vt, at which moment, the end of subinterval T3 is declared. The transition is now complete as far as the switch is concerned. But after that, during T4, the RC exponential discharge continues down to 10% of the initial gate drive amplitude. As before, driver dissipation occurs over T1 + T2 + T3 + T4, whereas crossover occurs during T2 + T3.
Ill. 13: Third Interval of Turn-off
Ill. 14: Fourth Interval of Turn-off
Ill. 15: Gate Charge Factors of a Mosfet
Gate Charge Factors
A more recent way of describing the parasitic capacitor-based effects in a mosfet is in terms of gate charge factors. In Ill. 15, we show how these charge factors, Qgs, Qgd, and Qg, are defined. On the right column of the table in the figure, we have given the relationships between the gate charge factors and the capacitances, assuming the latter are constants. Gate charge factors represent a more accurate way of proceeding, since the interelectrode capacitances are such strong functions of the applied voltage. However, our entire analysis of the turn-on and turn-off intervals so far has been implicitly based on the assumption that the interelectrode capacitances are constants. A possible way out of this, one that also helps reduce the error in our switching loss estimates, is detailed in Ill. 16, using the Si4442DY (from Vishay) as an example.
Basically, we are using the gate charge factors to tell us what the effective capacitances are (and the voltage swings from 0 to Vin). We see that the effective input capacitance (Ciss), for example, is about 50% greater than the single-point Ciss value that we would have read off from the typical performance curves (i.e. 6300 pF instead of 4200 pF). That factor accounts for the fact that as the voltage falls, the capacitance increases. Note that we could have calculated a scaling factor individually, for each capacitance. But it's simpler to use, say Ciss, to first find a "universal" scaling factor - and then apply it across the board to all the capacitances. In this manner, we arrive at the effective interelectrode capacitances quoted in Ill. 16. These are the values we should use for our switching loss calculations (in preference to those provided by directly reading off Ciss, Coss, and Crss from their curves). Note that for finding the scaling factor, if we had looked at Crss (Cgd) instead of Ciss, then we would find that the calculated effective capacitance is only 40% higher (than what we would read directly from the curves). So the scaling factor can, in general, be fixed at around 1.4 to 1.5 typically.
Ill. 16: Estimating the Effective Interelectrode Capacitances from the Gate Charge Factors (Si4442DY as an example)
We are switching 22 A at 15 V through a Si4442DY mosfet, at 500 kHz. The total pull-up drive resistance, by which the gate is driven by a pulse of amplitude 4.5 V, is 2 ohms. At turn-off, it's pulled-down (to source) by a total drive resistance of 1 ohm. Estimate the switching losses and the dissipation in the drive.
From Ill. 16, we have Cg = Cgs + Cgd = 6300 pF.
Turn-on: The time constant is Tg = R_drive × Cg = 2 × 6300 pF = 12.6 ns The time for the current to transit's
The time for the voltage to transit's
So the crossover time during turn-on is
The turn-on crossover loss therefore is
Pcross_turnon = 1/2 x Vin × Io × tcross_turnon × fsw
Pcross_turnon = 0.64 Watts
Turn-off The time constant is now Tg = R_drive × Cg = 1 × 6300 pF = 6.3 ns The time for the voltage to transit's
T2 = 8.858 ns
The time for the current to transit's
T3 = 1.198 ns
So the crossover time during turn-off is tcross_turnoff = T2 + T3 = 8.858 + 1.198 = 10 ns
The turn-off crossover loss therefore is:
pcross_turnoff = 0.5 × Vin × Io × tcross_turnoff × fs
pcross_turnon = 0.83 Watts So finally, the total crossover loss is Pcross = Pcross_turnon + Pcross_turnoff = 0.64 + 0.83 = 1.47 Watts Notice that we have not even used Cds so far! This particular capacitance does not affect the V-I overlap (since it's not connected to the gate). But it still needs to be considered! Every cycle, it charges up during turn-off, and then during turn-on it dumps its stored energy inside the mosfet. This is, in fact, the additional loss term that needs to be added to the crossover loss term, so as to get the total switching loss in a mosfet. Note that in low-voltage applications, this additional term may seem insignificant, but in high-voltage/off-line applications, it does affect the efficiency noticeably. Let us calculate what it's in our case:
So the total switching loss (in the switch) is Psw = P_cross + P_Cds = 1.47 + 0.025 = 1.5 Watts The driver dissipation is P_drive = V_drive × Qg × fsw = 4.5 × 36 × 10-9 × 5 × 105
= 0.081 Watts Note that typically, the above driver dissipation equation underestimates the actual driver dissipation by almost 20% - as can be confirmed by integrating the product of the drive current and the voltage across it, over each sub-interval. The reason for the error is simply the Miller plateau - because during this interval, some additional current (other than from the stored charge Qg), gets injected into the drive resistor. So our corrected driver dissipation estimate is 1.2 × 0.081 = 0.097 W. The driver supply rail current is 0.081/4.5 = 18 mA.
Applying the Switching Loss Analysis to Switching Topologies
Now we try to understand how our preceding analysis pertains to an actual switching regulator application - in particular, what "Vin" and "Io" are, with respect to the topology.
For a buck, we know that at turn-on, the instantaneous switch (and inductor) current is I_O × (1 - r/2), where r is the current ripple ratio, and "I_O" is the load current of the dc-dc converter. At turn-off, the current is I_O × (1 + r/2). Usually, we can ignore the current ripple ratio and take the current as IO for both the turn-on and the turn-off analysis. So the load current of the dc-dc converter, IO, becomes the same as the "Io" used so far in the switching loss analysis. Similarly, in a boost and buck-boost, the current "Io" in our switching loss analysis, is actually the average inductor current I_O/(1 - D).
Coming to the voltage across the mosfet when it turns OFF (i.e. "Vin" in the switching loss analysis) -- for the buck, this is almost equal to the input rail of the dc-dc converter VIN (a diode drop more in reality). Similarly, for a buck-boost, the voltage "Vin" is almost exactly equal to VIN + VO, where VO is the output rail of the dc-dc converter. For a boost, the voltage "Vin" is equal to VO, that's , the output rail of the converter. Note that if we are dealing with an isolated flyback, the voltage at turn-off really is VIN + VZ, where VZ is the voltage of the zener clamp (placed across the primary winding). However, at turn-on, the voltage across the mosfet is only VIN + VOR (VOR being the reflected output voltage, i.e. VO × nP/nS). In a single-ended forward converter, we have 2 × VIN at turn-off, and only VIN at turn-on. Note that in all cases discussed above, we are assuming CCM.
We have tabulated these results in Tbl. 1 for convenience.
Note that if we were in DCM, there is in principle no switching loss at turn-on - because there is no current flowing in the inductor by that time. At turn-off, the current at transition is I_PK = ?I, which can be found using V = L × ?I/?t.
Tbl. 1: Connecting the switching loss analysis with actual topologies
Worst-case Input Voltage for Switching Losses
We must return now to the all-important question - when we have a wide-input voltage range, what specific input voltage point represents the worst case for calculating switching losses? The switching loss equation is generically Psw = Vin · Io · t_cross · fsw Watts We note that see that in all cases, this loss depends on the product of Vin and Io. But by now, we know what Vin and Io are - from Tbl. 1. So we can analyze the situation for each topology as follows
++ For a buck, "Vin × Io" = VIN × IO. So the maximum loss will obviously occur at VINMAX.
++ For a boost, "Vin × Io" = VO × IO/(1 - D). So the maximum loss will occur at DMAX, that's , at VINMIN.
++ For a buck-boost, "Vin × Io" = (VIN + VO) × IO/(1 - D). We also know that D = VO/(VIN + VO). So plotting "Vin × Io," we get Ill. 17 (a typical case).
Note that the curve is symmetrical around D = 0.5 - and that's the point of minimum switching losses. Below that point, the voltage increases significantly, and above that, the current increases significantly. Either way, the switching losses increase as we move away from D = 0.5. Therefore, in general, we must first examine the input range of our application, and see which of its ends is furthest from D = 0.5. E.g., if in our application, the input range corresponds to a duty cycle range of 0.6 to 0.8, we need to do the switching loss calculation at D = 0.8, that's , at VINMIN. However, if the duty cycle range is say, 0.2 to 0.7, we need to do the calculation at D = 0.2, that's , at VINMAX.
Ill. 17: Switching Loss Variation with Respect to Duty Cycle, for the Buck-boost
How Switching Losses Vary with the Parasitic Capacitances
In Ill. 18, we have taken the Si4442DY, and "varied" its Ciss - just to see what can happen as a result of that. On the right vertical axis, we have the corresponding (estimated) switching loss. Note that in computing the loss curve, a "scaling factor" of 1.5 has been applied to the Ciss values given on the left vertical axis (though this isn't obvious).
The gray vertical dashed line (annotated "35 nC") represents the Si4442DY as it's. So under the stated conditions, we have an estimated switching loss of 2.6 W. If we increase Ciss by 50%, that's , 4200 pF to 6300 pF, we see that Qg will go up to about 47 nC, and the loss to 2.8 W only.
Note: In the actual calculations, using the scaling factor of 1.5, "4200 pF" is actually 6300 pF, and "6300 pF" is actually 9450 pF.
In Ill. 19, we take the Si4442DY, and "vary" its C_rss - just to see what can happen as a result of that. The gray vertical dashed line (annotated "35 nC") represents the Si4442DY as it's. So under the stated conditions, we have an estimated switching loss of 2.6 W. If we increase Crss by 50%, that's , 500 pF to 750 pF, we see that Qg will go up to about 39 nC only, but the loss goes up to 3.1 W.
Ill. 18: Varying the C_iss of the Si4442DY
In other words, Qg will certainly affect driver dissipation, but it's not necessarily a good indicator of the switching losses - it's more helpful to try and minimize Qgd (or Crss) when selecting mosfets, rather than just looking for a "low-Qg" mosfet.
Note: In the worked example, we had estimated the losses to be 1.5 W. There we had a pull-up of 2 ohms, and a pull-down of 1 ohm. Whereas in Ill. 18, we have basically doubled the pull-up and pull-down resistors. However, the switching loss has not doubled - it's only 73% more.
Ill. 20: Varying the Threshold Voltage of the Si4442DY, and the Drive Resistances (keeping pull-up resistance fixed).
Ill. 21: Varying the Threshold Voltage of the Si4442DY, and the Drive Resistances (keeping total drive resistance i.e. pull-up + pull-down, fixed)
Optimizing Driver Capability vis-à-vis Mosfet Characteristics
In Ill. 20, we have two separate graphs. The one on the left has a fixed pull-up of 4 ohms. On the x-axis, we are therefore, in effect, varying only the pull-down. So if for example, the x-axis is at 2, the pull-down resistor is 4 ohms/2 = 2 ohms. If the x-axis is at 4, the pull-down resistor is at 4 ohms/4 = 1 ohm. We see that as expected, the losses decrease as the pull-down is improved. We also see the effect of "varying" the threshold voltage. So, lower threshold voltages also help lower the switching losses - provided the pull-down isn't too "weak." On the right graph similarly, we have the results for a fixed pull-up of 10 ohms. We can thereby estimate the effect of varying the pull-up too, on the overall losses.
Finally, in Ill. 21, we are keeping the pull-up + pull-down constant, as we vary the ratio of the pull-up and pull-down resistors. This is from the IC designer's viewpoint - suppose he or she has roughly allocated a certain die area for the driver stage, say simplistically fixed the pull-up + pull-down. Then the question is - how should the available drive capability be distributed between the pull-up and the pull-down sections. E.g., if pull-up + pull-down = 6 ohms, is it better to split this as - pull-up = 4 ohms and pull-down = 2 ohms, or say, pull-up = 3 ohms and pull-down = 3 ohms, or pull-up = 2 ohms and pull-down = 4 ohms, and so on? We see that the answer to that depends on the threshold voltage. So we need to have an idea of the mosfets we are planning to use, before we decide on the optimum ratio. From Ill. 21 we see that if the threshold is greater than 2 V, improving the pull-up (at the expense of the pull-down) will help, and so for example - pull-up = 4 ohms and pull-down = 2 ohms will be preferable to pull-up = 5 ohms and pull-down = 1 ohm. However, if the threshold voltage is below 2 V, we see that the reverse is true - so now, improving the pull-down (at the expense of the pull-up) will help.
Note: Some vendors provide a rather wide range ("MIN" to "MAX") for threshold voltage. Often, they don't even provide a "TYP" value. But surprisingly, some don't even provide the threshold voltage at all! They simply state that their mosfet is "capable of 4.5 V drive" (as for example most of the mosfets from renesas.com).
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