Troubleshooting Analog Circuits--Analog vs. Digital

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A Never-NeverLand?

Previous sections have dealt with circuit elements and circuits usually thought of as purely analog. Now we turn to an area that confounds and frightens all too many engineers--the boundary between the analog and digital worlds. Armed with a solid theoretical foundation and the insights presented here, you can keep your journey into the analog/digital interface from seeming like a visit to an unreal world.

Many classes of circuits are neither entirely analog nor entirely digital. Of courses as an analog engineer, I don't have a lot of trouble thinking of all circuits as analog.

Indeed, when problems develop in circuits containing both analog and digital elements, finding a solution is more likely to require that you summon your analog expertise than your digital knowledge. Timers, D/A and A/D converters, V/F and F/V converters, and S P circuits all fall right on the boundary line between the analog and digital worlds. Digital ICs have more than a few analog subtleties. And even multiplexers, which you may have thought of as purely analog, have some quirks that result from their close association with the digital world.

Time for Timer

A timer is basically a special connection of a comparator and some logic, which is usually built with analog circuit techniques. The familiar 555 timer can do a lot of useful things, but it sure does get involved in a great deal of trouble. I'll treat the most classical fiascoes.

For one thing, people try to make timers with the crummiest, leakiest--usually electrolytic capacitors. Then they complain because the timers are not accurate or their timing isn't repeatable. Some people insist on building timers to run for many seconds and then have trouble tweaking the time to be "exactly right." Sigh. These days I tell people, "Yes, you could make a 2-minute timer with an LM555 or a 10 minute timer with an LM322, but that would be wrong." Instead, you could make a simple 4-Hz oscillator using one-quarter of an LM324 or LM339 and cheap, small components. This oscillator can drive a CD4020 or CD4040; the last output of that counter, Q12 or Q14, can time very accurately and conveniently.

Such an arrangement is cheaper and much more accurate and compact than what you get if you blow a lot of money on a 47 pF polyester capacitor for a long-interval timer, or put up with the leakages of a tantalum capacitor, which no manufacturer wants to guarantee. In addition, in just a few seconds, you can trim the moderate frequency oscillator by looking at an early stage of the divider; trimming a long interval timer can take hours. The CMOS counters are inexpensive enough, and these days for 2- to 20-minute timer applications, I can usually convince customers not to buy the linear part. The LM555 data sheets tell you to avoid timing resistors with values higher than 20 M-ohm. Nowadays, though, you can get a CMOS version (LMC555 or equivalent) or use a CMOS comparator or a CMOS op amp to work at 100 M-ohm or more. Just be careful about board leakage and socket leakage-as you would with a high-impedance op-amp circuit. Then you can use a smaller, higher-quality capacitor.

Furthermore, it is a nontrivial statement that not all 555s work similarly; some manufacturers' 555s have different internal circuits and different logic flow charts.

So be careful to check things out-555s from different manufacturers can act quite differently.

At high speeds, the timers don't just respond in a time 0.693 R x C; the response time is more like 0.693 R x (C + C_STRAY) +T_DELAY. Most books never mention this fact--most data sheets don't, either. So, although you can usually get a fast timer circuit to function, to get it to work the way you want it to, you still have to be careful. These designs are not always trivial, and Ref. 1 may help you avoid some pitfalls. A timer is, after all, just an aggregation of parts that includes a comparator, so many of the techniques you use with comparators work with timers, and vice versa.

Digital ICs: Not Purely Digital

Although timers are partly digital, the more classic digital ICs perform purely logical functions. Nevertheless, in the hands of a clever "linear" designer, some digital ICs can be very useful for performing analog functions. For example, CD4066 quad analog switches make excellent low-leakage switches and a 74C74 makes an excellent phase detector for a Phase-Locked Loop (Ref. 2). And not only is the price right-so is the power drain. Even when ordinary CMOS ICs aren't fast enough, you can often substitute a high-speed CMOS or 74ALS or 74AS counterpart to get more speed. I won't belabor the point; instead, I'll go straight to the litany of Troubles and Problems that you--whether an analog or a digital designer--an encounter with digital ICs.

First, unless proven otherwise, you should have one ceramic power-supply bypass capacitor in the range 0.02 to 0.2 uF--or even 1 uF, if the IC manufacturer requires it--for each digital IC, plus a tantalum capacitor in the range 2 to 10 uF for every two, three, or four ICs. The ceramic capacitors provide good local high-frequency bypassing; the tantalum parts damp out the ringing on the power-supply bus. If you can't use a tantalum capacitor, you can use 10 or 20 uF of aluminum electrolytic, or if you are desperate you can try a 1 or 2 uF extended-foil Mylar unit in series with a 1-ohm carbon resistor, to provide the needed lossiness. If your linear circuit really depends on clean, crisp digital outputs (CMOS outputs make dandy square-wave generators, as long as the power supply isn't ringing and bouncing) you may even want more bypassing-possibly hundreds of microfarads.

Floating Inputs Can Leave You at Sea

On TTL parts, you can leave an unused input floating and it will normally go HIGH: on CMOS, you must tie unused inputs (such as the preset and clear inputs of a flip-flop) to the positive supply or ground, as appropriate. Otherwise, these inputs will float around and give you the screwiest intermittent problems. Also, when these inputs float, for example, on unused gates, they can cause considerable unwanted power drain and self-heating.

With CMOS, people used to tell you that you can use an inverter as an amplifier by tying a few megohms from the input to the output. At low voltages, you can make a mediocre amplifier this way, but when the supply voltage is above 6V, the power drain gets pretty heavy and the gain is low. I don't recommend this approach for modem designs.

Many years ago, people used to tie the outputs of DTL or open-collector TTL gates together to form a "wired OR" gate. This practice has fallen into disrepute as it supposedly leads to problems with troubleshooting. I don't know what other reason there is for not doing it, except to avoid acting like a nerd. However, an open-collector output with a resistive pull-up is slower than a conventional gate and wastes more power.

A couple engineers chided me, that if you let TTL or DTL inputs float, that may appear to work OK for a while, but when you get all the signal busses packed in together, the unused inputs may be driven to give a false response--not consistently but intermittently. So, it is bad practice to let your TTL inputs float. It is also not quite correct to tie those inputs to the +5-V bus. Tie them up toward +5V through 1 k-ohm.

Then a momentary +7V transient on the supply bus may do less harm, less damage.

When digital-circuit engineers have to drive a bus for a long distance, say 20 or 30 inches, they use special layouts, so the bus will act like a 75 ohm or 93 ohm stripline.

They also add termination resistors at one or both ends of the bus to provide damping and to cut down on reflections and ringing. When you have to drive long lines in an analog system, you must do the same. Note that for really fast signals, digital designers don't even lay out their PC traces with square comers; they bend the foil around the comer in a couple of 45-degree turns. Many digital engineers are not just bit pushers; they've been learning how to handle real signals in the real world. They are actually pretty expert in some analog techniques, and analog engineers can learn from them.

Perfect Waveforms Don't Exist

Even though many digital engineers are familiar with real problems, they often sketch the waveforms from gates and flip-flops showing nice, crisp, vertical rises and showing the output of a gate changing at the same time as the input. But smart engineers are aware that when it comes down to the fine print, they must be prepared to admit that these waveforms have finite rise-times and delays. These nit-picking details are very important when your signals are in a hurry.

For example, if the data input of a D flip-flop rises just before you apply the clock pulse, the output goes high. If the data input rises just after you apply the clock pulse, the output goes low. But if the D input moves at just the wrong time, the output can show "metastability"--it can hang momentarily halfway between HIGH and LOW and take several dozen nanoseconds to finally decide which way to go. Or, if the data comes just a little earlier or later, you might get an abnormally narrow output pulse a "runt pulse." When you feed a runt pulse to another flip-flop or counter, the counter can easily respond falsely and count to a new state that might be illegal. Thus, you should avoid runt pulses and make sure that you don't clock flip-flops at random times. Fig. 1a contains an example of a D flip-flop application that can exhibit this problem. When the comparator state changes at random times, it will occasionally change at precisely the wrong time-on the clock's rising edge-making the output pulse narrower or wider than normal. In certain types of A/D converters, this effect can cause nonlinearity or distortion. A good solution is to use a delayed clock to transfer the data into a second flip-flop, as in Fig. 1b.

A glitch is an alternate name for a runt pulse. A classic example of a glitch occurs when a ripple counter, such as a 7493, feeds into a decoder, such as a 7442. When the counter makes a carry from 0111 to 1000, for a few nanoseconds the output code will be 0000, and the decoder can spit out a narrow pulse of perhaps 6-8 ns in duration corresponding to 0000. Even if you are observing with a good scope, such a pulse can be just narrow enough to escape detection. If the decoder were merely feeding an LED display, you would never see the sub-microsecond light pulse, but if the decoded output goes to a digital counter, a false count can occur. In digital systems, engineers often use logic analyzers, storage scopes, and scopes with very broad bandwidths to look for glitches or runt pulses and the conditions that cause them. In analog systems, you may not have a logic analyzer, but these nasty narrow pulses often do exist, and you have to think about them and be prepared to look for them.

Another thing to know about digital ICs is that many CMOS ICs have the same pinouts as TTL parts. For example. the 74193,74LS193, and 74C193 have the same pinouts. On the other hand, some of the older CMOS parts have pinouts that differ from those of similarly numbered TTL devices. The 74C86's pinout is the same as the 74L86's but differs from the 7486's. Beware!

FIG. 1. Runt pulses cause problems in this simple ADC (a). The comparator state changes at random times. Occasionally, the state will change at precisely the wrong time--on the clock's rising edge-making the output pulse narrower or wider than normal. You can solve the problem by using two flip-flops with the clocks separated by a delay.

A list of all these ICs with nonstandard pinouts, are avail. via Google. Search "ICs with nonstandard pinout".

Similarly, some CMOS devices have many--but not all--of their functions in common with those of their TTL counterparts. For example, the 74C74 has the same pinout and 95% of the same functions as the TTL 7474. Both follow mostly the same truth table, except that when you pull both the preset and clear inputs low, the TTL device's outputs (Q and q) both go LOW, whereas the CMOS part's outputs both go HIGH. If anybody has a complete list of such differences, I'd love to see a copy.

In some cases you can buy a buffered gate (CD4001BN), an unbuffered gate (CD4001), an unbuffered inverter (MM74HCU04), or a buffered inverter (MM74HC04). Sometimes, you can buy one part number and get an unbuffered part from one vendor and a buffered one from another. Of course, the unbuffered parts are faster with light capacitive loads, but the buffered ones are faster with heavy loads.

So if you have a critical application, be aware that substituting different vendors' parts can mess up your circuit. Be careful when interfacing from linear ICs into digital ones. For example, an LM324 running on a single 5-V supply doesn't have a lot of margin to drive CMOS inputs, but an op amp running on +/- 5 or +/- 10 V would need some kind of attenuation or resistive protection to avoid abusing the logic-device inputs (FIG. 2).

Likewise, it's considered bad form to overdrive the inputs of digital ICs just because they are protected by built-in clamp diodes. For example, you can make a pulse generator per FIG. 3, but it's considered bad practice to drive the inputs hard into the rail and beyond, as you will if the capacitance is more than 0.01 uF or the power supply voltage is higher than 6V. The circuits in FIG. 4 do as good a job without overdriving the inputs.

74LS75s are very touchy when you pull their inputs below ground even micro-momentarily, and give false readings for a long time. It sounds to me that there are probably currents being injected into tubs, as with an LM339: Thus, these are unhappy One reader cautioned me that some LS-TTL parts such as DM74LS86 and parts if you overdrive the inputs much below ground.

FIG. 2. Driving logic from an op amp operating from the usual large supply voltages requires an attenuator between the amplifier and the logic IC. The equations show how to calculate the attenuator ratios.

FIG. 3. This CMOS pulse generator (a) is not recommended because, with the values shown, it overdrives the gate inputs excessively--as the waveforms of (b) indicate.

FIG. 4. The addition of resistors to the circuit of FIG. 3 (a) helps reduce overdrive, but the addition of diode clamps in the shunt leg of the attenuators (b) is even more effective. If you have two 2-input NAND gates available, the circuit of (c) is the best implementation.

A Time to Ask Probing Questions

A number of years ago, I was watching the negative transition of an ordinary TTL gate, and I was especially concerned by the way it was overshooting to -0.4V. I set up an attenuator with 1 pF in the input leg ( FIG. 5), and was astounded to see that if I looked at the waveform with an ordinary (11-pF) probe, the overshoot occurred, but if I disconnected the probe from the gate output and connected it to the attenuator output, the overshoot went away. So, even if you use a fairly high-impedance probe, you should always be prepared for the possibility that by looking at a signal, you can seriously affect it-even if what you're looking at is as mundane and supposedly robust as a TTL output. Consequently, you should be prepared to build your own special-purpose probes, so you can see what's really going on.

When I work with digital ICs, I would be easily confused if I did not sketch the actual waveforms of the ICs to show their relationships to each other. So I sketch these waveforms on large sheets of quadrille paper (1/4-in. grid) to produce something I call a "choreography" because it maps out what I want all the signals to do and exactly where and when I require them to dance or pirouette.... When the system gets big and scary, I sometimes tape together two or three or four sheets horizontally and as many sheets as I need vertically. Needless to say, I am not very popular when I drag one of these monsters up to the copying machine and try to figure out how to make a copy. FIG. 3b is a small example.

NOTE, when I first published this FIG. 3b in EDN magazine in 1989, the sketch was printed with an error; some of the pulses were positioned at the wrong time. And did EDN make the error? Not at all! I drew it wrong and the error wasn't caught until after publication when a kid engineer suggested it might be erroneous.

He was right. How embarrassing. It would have been even worse if a whole lot of people had called to correct me. That just goes to show, if you stand on a big soapbox and rant and holler, people will often think you know what you are talking about.

They stop looking for mistakes... and that's a mistake. Bigwigs make mistakes--and wanna-be big-wigs, too. Embarrassing....

Maybe the guys who design really big digital ICs can get along without this choreography technique; maybe they have other mnemonic tools, but this one works for me. I first developed this approach the time I designed a 12-bit monolithic ADC, the industry's first, back in 1975. I had this big choreography, about 33 inches square, and the circuit worked the first time because the choreography helped me avoid goofing up any digital signals. Right now I'm working on a system with one choreography in nanoseconds and tenths of nanoseconds linked to a second one scaled in microseconds and a third one scaled in seconds. I hope I don't get lost.

Of course, this tool is partly for design, but it's also a tool for troubleshooting and for planning, so you can avoid trouble in the first place.

D/A Converters Are Generally Docile

D/A converters are pretty simple machines, and they can usually give excellent results with few problems. If the manufacturer designed it correctly and you are not misapplying it, a DAC usually won't cause you much grief.

One area where DACs can cause trouble, however, is with noise. Most DACs are not characterized or guaranteed to reject high-frequency noise and jumps on the supply voltages. In some cases, the DC rejection can be 80 or 100 dB, but high-frequency noise on a supply can come through to the output virtually unattenuated. So you must plan your system carefully. It might be a good idea, in a critical application, to use a completely separate power-supply regulator for your precision DAC. At least you should add plenty of good power-supply bypass capacitors right at the power-supply pins--ceramic and tantalum capacitors.

FIG. 5. An ordinary high-impedance probe can cause TTL outputs to appear to overshoot when you look at them, but not when you are not looking at them. You can eliminate this effect by making your own very-high-impedance probe, that presents only a 1-pF capacitive load.

D/A Converters Are Generally Docile

An ordinary high-impedance probe can cause TTL outputs to appear to overshoot when you look at them, but not when you are not looking at them. You can eliminate this effect by making your own very-high-impedance probe, that presents only a 1-pF capacitive load.

FIG. 6. (coming soon) The author irritates co-workers when he carries one of his large "choreographies" to the photocopier and tries to figure out how to duplicate such a large drawing. In fact, some say that he irritates co-workers most of the time.

Sometimes when you feed signals to a DAC without passing them through buffers, the noise, ringing, and slow settling of the digital signals can get through to the analog side and show up on the DAC output. Nobody has a spec for rejection of the noise on DAC bit lines in either the HIGH or LOW state. Maybe vendors should specify this parameter, because some DACs are good and some aren't. I even recall a case where I had to preload the TTL outputs of a modular DAC's internal storage register with a 2 k-ohm resistor from each line to ground. Otherwise they would overshoot when going HIGH and then recover with a long slow tail, an attenuated version of which would then appear on the DAC output.

On-chip buffers at a DAC's input can help cut down feedthrough from the bit lines to the analog output, but will not completely eliminate it. The bus can move around incessantly, and capacitive coupling or even PC-board leakage will sometimes cause significant crosstalk into the analog world. Even IC sockets can contribute to this noise. If you could prove that such noise wouldn't bother your circuit, you could forget about it. The problem is that you can only make meaningful measurements of such effects on an operating prototype-computer modeling isn't going to simulate this.

Multiplying DACs are popular and quite versatile. However, a multiplying DAC's linearity can be degraded if the output amplifier's offset voltage isn't very close to zero. I've heard this degradation of linearity estimated at 0.01% per millivolt of offset. Fortunately, low-offset op amps are pretty cheap these days. At least a low-offset op amp is cheaper than a trim-pot.

Another imperfection of any multiplying DAC is its AC response for different codes. If you put in a 30-kHz sine wave as the reference, you shouldn't really be surprised if the gain from the reference to the output changes by more than 1 LSB when you go from a code of 1000 0000 to a code of 0111 1111. In fact, if the frequency is above 5 kHz, you may find a 0.2% or larger error because the multiplying DAC's ladders, whose attenuation is a linear function of the input code at DC, become slightly nonlinear at high frequencies due to stray capacitance. The nonlinearity can be 0.2%, and the phase change as you vary the input code can exceed 2 degrees , even with a 5-kHz reference. So don't let these AC errors in multiplying DACs surprise you.

Another problem with DACs is the output glitch they can produce when going from one code to an adjacent one. For example, if a DAC's input code goes from 1000 0000 to 0111 1111 and the delay for the rising bits is much different from that for the falling bits, the DAC output will momentarily try to go to positive or negative full scale before it goes to a value corresponding to the correct code. Though well-known, this problem is a specialized one. One possible solution calls for precisely synchronous timing. Multiple fast storage registers can also help to save the day. But if the best synchronous timing is not good enough, a deglitcher may be the solution.

ADCs Can Be Tough and Temperamental

Like DACs, many A/D converters (ADCs) do exactly what they are supposed to, so what can go wrong? Most problems involve a characteristic that is mentioned on too few data sheets: Noise. When an analog signal moves slowly from one level to another, it would be nice if the ADC put out only the code for the first voltage and then, at the appropriate threshold, began to produce only the code for the other voltage. In practice, there is a gray area where noise causes codes to come up when they shouldn't. On a good ADC, the noise can often be as low as 0.1 or 0.05 LSB p-p. But when you come to a worst-case condition (which with successive-approximation converters often occurs at or near a major carry-for example, where the output changes from 1000 0000 to 0111 11111, the noise often gets worse, sometimes climbing to 0.5 LSB p-p or more. I wouldn't want to buy an ADC without knowing how quiet it was. I'd have to measure the noise myself, as shown in FIG. 7, because virtually nobody specifies it. That's not to say all ADCs are bad, just that manufacturers don't make much noise about noise. Ron Knapp of Maxim wrote a nice explanation of this ADC noise measurement technique in EDN recently (Ref. 3).

I recommend his article on this subject.

Most ADC data sheets spell out that the only correct way to test or use an ADC is with the analog signal's ground, the digital supply's ground, and the analog supply's ground tied together right at the ground pin of the ADC. If you don't or can't interconnect the grounds at the specified point, all bets are off.

FIG. 7. A reference source, a triangular-wave generator, and a scope are the major building blocks of an ADC cross-plot tester (a) that can reveal how much noise a converter adds to the signal it is digitizing. In (b) the noise performance is ideal, whereas in (c) it is merely acceptable. In (d) the noise performance is unacceptable.

With ADCs, Paper Designs Aren't Adequate

On one 10-bit ADC I designed, when the customer found some problems that I couldn't duplicate in my lab, I bought one plane ticket for me and one for my best scope. After a few hours we arrived at the scene, and in less than an hour I had the problem defined: The customer expected our converter to meet all specs with as much as 0.2 VDC plus 0.2 VAC, at frequencies as high as 5 MHz, between the analog ground and the digital ground! Outrageous! Amazingly, our architecture was such that by deleting one resistor and adding one capacitor, I could comply with the customer's wishes. Most ADCs couldn't have been adapted to work-the customer was fantastically lucky that I had used a weird design that was amenable to this modification. My design was a high-speed integrating converter with an input voltage-to-current converter that just happened to be capable of rejecting wideband noise and DC offsets between grounds.

The general lesson is that any ADC system is nontrivial and should be engineered by actually plugging in some converter circuits. "Paper designs" usually don't hold water in ADC systems.

To beat the requirement that every ADC have its own set of power supplies dedicated exclusively to powering just the single converter, you may want to bring power to your PC boards in unregulated or crudely regulated form, and then put a small regulator right near each ADC. These small regulators (whether LM320L15, uA78L05, LM317L, or whatever) do not have a high power-supply rejection ratio at high frequencies.

You can resolve that problem with decoupling, so you have a chance to make the scheme work. I hasten to point out, however, that I haven't actually built such a system myself very often.

Don't Let Ground Loops Knock You for a Loop

The need for multiple (separate) power supplies, or at least multiple regulators, comes, of course, from the many paths taken by ground currents flowing to and from the power supplies. If you don't keep these paths scrupulously separate, the ground loops can cause bad crosstalk between various parts of the system-low-level analog, high-power analog, and digital. So be very careful to avoid ground loops when you can. Although the electrical engineering faculty at your local university might not agree, a general solution to the ground-loop problem would be an excellent subject for a PhD thesis. If you write such a dissertation, please don't forget to mail me a copy.

Some successive-approximation ADCs have separate buffers feeding their output pins, but other designs try to save money, parts, power, or space by using the internal registers to drive both the internal DAC and the output pins. In this case, external loads on the outputs can cause poor settling and noise and can thus degrade the performance of the converter. If you're using ADCs, you should find out if the outputs are connected directly to the DAC. Sometimes, as previously mentioned, a preload on each bit output can help to accelerate settling of an ADC's internal DAC. After all, TTL outputs must be able to drive more current than their DC specs state-they have to meet their AC specs.

VFCs and FVCs Frequently Find Favor

The voltage-to-frequency converter (VFC) is a popular form of ADC, especially when you need isolation between the analog input and digital outputs. You can easily feed a VFC's output pulse train through an optocoupler to achieve isolation between different ground systems. The VFC can cover a wide range with 14 to 18 bits of dynamic range. The less expensive VFCs are slower; the faster ones can be expensive.

Most VFCs have excellent linearity, but the linearity depends on the timing capacitor having low dielectric absorption. Teflon makes the best VFC timing capacitors, but polystyrene, polypropylene, and ceramic capacitors with a C0G characteristic are close behind. (Refer to the LM131LM331 data sheet, for examples and notes.) Trimming a VFC to get a low temperature coefficient is not easy because the overall temperature coefficient depends on several components, including the reference, as well as various timing delays. See Ref. 4 for VFC trimming procedures or, at least, to appreciate how much effort is involved when you buy a well-trimmed unit.

The Other Way Back

Frequency-to-voltage converters (FVCs) are often used as tachometers or in conjunction with a VFC and an optoisolator to provide voltage isolation in an analog system.

FVCs are about as linear as VFCs and about as drifty, so the temperature trimming problem is the same as for a VFC. One exception is if you're using cascaded VFC/FVC pairs in which both circuits are in the same location and at the same temperature.

In that case, you can often get by with trimming only one of the pair. or by just making sure the TCs match! Another problem with FVCs is that you often want the response to be as fast as possible but need to keep the ripple low. The design of a filter to accomplish both objectives will, of course, be a compromise. My rule of thumb is that you can keep the ripple down to about 0.01% of the V_full-scale, but with the simplest filters, you must keep the carrier at least 100 times the F_min. With more sophisticated filtering, such as two Sallen-Key filters cascaded, the -3-dB point can be 1/10 of the slowest carrier. For example, with a carrier frequency in the range 5-10 kHz, the signal can go from DC to 500 Hz (Ref. 5). If you need still faster response, see Ref. 2, which shows in a cookbook circuit how to use a simple phase-locked loop to make a surprisingly quick FVC.

S/H Circuits: Electronic Stroboscopes

A VFC produces an output proportional to the average value of its analog input during the conversion. If you need to digitize rapidly changing signals, for example, to reconstruct waveforms in the digital domain, you need a different type of ADC and you almost always have to precede it with a sample-and-hold circuit. Designing S/H circuits is a complicated, challenging endeavor. Meeting exacting specs often requires an expensive module or hybrid circuit. A major problem of S/H circuits is dielectric absorption, or "soakage," in the hold capacitor (Ref. 6). If you need to run a relatively short sample time with a long hold time and if the new output voltage can vary considerably from the previous sample, the soakage may be your biggest problem. For example, if an S/H circuit acquires a new voltage for 5 ps and then holds it for 500 ps, you can tell approximately what the previously held signal was because the new V,,, can shift by 2-3 mV--the amount and direction depend only on the value of the previous signal. And that's for an expensive Teflon hold capacitor--most other capacitors have soakages three to five times worse. If the timing, frequency, and reprate don't change, you may be able to add a circuit to provide some compensation for the soakage (Ref. 7); but the problem isn't trivial, and neither is the solution.

Cascading two S/H circuits--a fast one and a slow one with a big hold capacitor--won't help the soakage but will tend to minimize the problem of leakages.

Some people wish that a S/H circuit would go from sample to hold with a negligible jump, or "glitch." Although you can build such a circuit, it's a lot more difficult than building a more conventional S/H circuit. You usually find glitch-free S/H circuits only in "de-glitchers," which are more expensive than most S/H circuits. Several module and hybrid manufacturers provide this kind of precision device. Even though it doesn't settle out instantly, a deglitcher is fast and consistent in its settling.

However, it still does take some time to settle within 5 mV.

Aperture Time Still Causes Confusion

There's one area of specsmanship where the S/H circuit is clouded in confusion.

That area is the aperture-delay specification. (Maybe someday I'll write a data sheet and drive away the cloud. Ask me for a data sheet on the LF6197... ) One technique for measuring and defining aperture delay is to maintain V1, at a constant level and issue the HOLD command. If after a short delay, V1, jumps by a few volts, the smallest spacing between the HOLD command and the V1, jump that causes no false movement of V,,, is one possible definition of the t_APERTURE-DELAY.

Another way of defining and measuring aperture delay is to let V1, move smoothly at a well-defined rate. Shortly after you issue the command to switch the circuit to the HOLD mode, Vout stops changing. The value at which V_out stops corresponds to the value of V1, at a particular point in time. You can define the aperture delay as the difference between this point and the time at which the mode-control signal crossed the logic threshold. The uncertainty in the value of the aperture delay is then the aperture uncertainty. Depending on how the circuit was optimized, that delay can be positive or negative or practically zero--perhaps only 1 ns or less. Now, will the real definition of aperture time please stand up? I think that both of the characteristics I have described are of interest to people at different times. But, how can you avoid the problem of a person expecting one of these characteristics and actually getting the other? I invite your comments on who wants to buy which characteristic, and where to find a definition. I've looked in military specs and at many data sheets, and the issue still seems pretty unclear.

Another instance in which a S/H circuit can have trouble is when its output is connected to a multiplexer, for example, when multiple S/H circuits drive a single ADC to achieve simultaneous sampling of many channels of dynamic analog data. If the multiplexer, which had been at a voltage of, say, +10 V, suddenly connects to the output of a S/H circuit whose output is at -10 V, the circuit's output will twitch and then may jump to a false level because the multiplexer will couple a little charge through the S/H circuit into the hold capacitor. The industry-standard LF398 is fairly good at driving multiplexers, but if you get a big enough capacitance on the multiplexer output--perhaps 75 pF--and it's charged to a voltage more than 10V away from the S/H circuit's output voltage, even the LF398's output can jump. I don't have a real solution for this problem, but if you are aware that it can happen, at least you won't tear out all your hair trying to guess the cause. You will recognize the problem, and then tear out your hair. About all you can do is try to minimize the capacitance on the output of the multiplexer. One way to do this is by using a hierarchical connection of sub-multiplexers.

Not Much Agreement on Acquisition-Time Definition

Another area of S/H-circuit confusion is acquisition time. I have seen at least one data sheet that defined acquisition time as the time required to go from HOLD to SAMPLE and for the output to then settle to a value corresponding to a new value of V1, in the SAMPLE mode. However, the outputs of many S/H circuits can settle to a new DC value faster than the hold capacitor charges to the correct value. If the S/H doesn't have to go back to HOLD, the data may give false results, even if the output seemed to give the correct answer when it was still in SAMPLE mode. To avoid confusion, we define acquisition time as the pulse width required for precise sample-and-hold action. If the circuit SAMPLES and settles and then goes into HOLD and gives you the wrong answer, the SAMPLE pulse should have been wider-right? Right.

There may be some S/H circuits whose output voltage won't change if you switch them to the HOLD mode as soon as their output reaches a value that corresponds to a new V_in. But if I had an analog switch that couldn't hold at all, I could still get it to "acquire" a signal according to the data-sheet definition just cited. I consider the test implied by that definition to be too easy. I believe some users and manufacturers in this field agree with my definition, but the situation isn't really clear. (I would appreciate reader comments. You folks are getting all sorts of good ideas from me, and if you have some good comments, it's only fair that you bounce them off me.)

E Pluribus Unum: The Multiplexer

Another type of circuit that depends on analog switches is the analog multiplexer.

As mentioned already, a multiplexer can draw big transients if you suddenly connect it across big signals at low impedances. So be careful not to overdo operating a multiplexer in this manner, as excessive current could flow and cause damage or confusion. It's well known that multiplexers, like most other forms of analog switches, are imperfect due to leakages, on-resistance, and response time. But they are popular and won't give you much trouble until you turn the power supplies OFF and keep the signals going. I recall that in the past few years, at least one or two manufacturers have brought out new designs that could survive some fairly tough over-voltages with the power removed. I'm not sure what the designs involved other than adding thin-film resistors and diode clamps on the inputs--ahead of the FET switches. But if you add discrete resistors ahead of any monolithic multiplexer's inputs, the resistors can help the multiplexer survive the loss of power.

One other problem with multiplexers is that you don't have a whole lot of control over the break-before-make margin. And if you should want make-before-break action, I don't think it's an available option. So, sometimes you may have to "roll your own" multiplexer.

If your signal levels are less than 15 V p-p, you may be able to use the popular CD4051 and CD4053 multiplexers and the CD4066 CMOS analog switches, which are inexpensive and quick and usually exhibit low leakage. However, if you need a guarantee of very low leakage, you will have to test and select the devices yourself, as many people do.

Digital Computers

To avoid making unpleasant comments, I will simply say that I hope somebody else writes a good book on troubleshooting these.

Software NO comment.

So, we take leave of the analog-digital world-sort of. In the next section, we'll visit another area of great importance to analog/digital electronics, but it is a purely linear region, perhaps the most purely linear: References. Armed with knowledge about references, we'll move on to the troubleshooting of power electronics, including switching regulators.


1. Jung, Walter, 555 Timer Cookbook, Howard Sams and Co, Indianapolis, IN, 1977.

2. Pease, Robert A., "Wideband phase-locked loops take on F/V-conversion chores," EDN, May 20, 1979, p. 145. (Also available as AN-210 in NSC's Linear Applications Book, 1986, 1989, etc. "New Phase-locked-loops Have Advantages as Frequency-to-Voltage Converters (and more).")

3. Knapp, Ron, "Evaluate your ADC by using the cross-plot technique," EDN, November 10, 1988, p. 25 1.

4. Pease, R. A., "Versatile monolithic V/Fs can compute as well as convert with high accuracy," Electronic Design, December 6, 1978, p. 70. (Also available as Appendix D in National Semiconductor Corp. Linear Applications Handbook, Santa Clara, CA, 1986, p. 12 13.)

5. Pease, R. A., "V/F-converter ICs handle frequency-to-voltage needs," EDN, March 20, 1979,

p. 109. (Also available as Appendix C in National Semiconductor Corp. Linear Applications Handbook, Santa Clara, CA, 1986, p. 1207.)

6. Pease, R. A., "Understand capacitor soakage to optimize analog systems," EDN, October 13, 1982, p. 125.

7. National Semiconductor Corp., Linear Databook 2, Santa Clara, CA, 1986, p. 5-5.

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